SLUSC89 November   2015 TPS40210-EP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Soft-Start
      2. 7.3.2  BP Regulator
      3. 7.3.3  Shutdown (DIS/EN Pin)
      4. 7.3.4  Minimum On-Time and Off-Time Considerations
      5. 7.3.5  Setting the Oscillator Frequency
      6. 7.3.6  Synchronizing the Oscillator
      7. 7.3.7  Current Sense and Overcurrent
      8. 7.3.8  Current Sense and Subharmonic Instability
      9. 7.3.9  Current Sense Filtering
      10. 7.3.10 Control Loop Considerations
      11. 7.3.11 Gate Drive Circuit
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Near Minimum Input Voltage
      2. 7.4.2 Operation With DIS/EN Pin
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Duty Cycle Estimation
        2. 8.2.2.2  Inductor Selection
        3. 8.2.2.3  Rectifier Diode Selection
        4. 8.2.2.4  Output Capacitor Selection
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  Current Sense and Current Limit
        7. 8.2.2.7  Current Sense Filter
        8. 8.2.2.8  Switching MOSFET Selection
        9. 8.2.2.9  Feedback Divider Resistors
        10. 8.2.2.10 Error Amplifier Compensation
        11. 8.2.2.11 RC Oscillator
        12. 8.2.2.12 Soft-Start Capacitor
        13. 8.2.2.13 Regulator Bypass
        14. 8.2.2.14 Bill of Materials
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Related Devices
    2. 11.2 Documentation Support
      1. 11.2.1 References
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

  • For the maximum effectiveness from C9, place it near the VDD pin of the controller. Excessive high frequency noise on VDD during switching degrades overall regulation as the load increases.
  • Keep the output loop (Q1-D1-C12-R11) as small as possible. A larger loop can degrade current limit accuracy and increase rediated emissions.
  • For best current limit accuracy keep the ISNS filter components C10 and R10 near the ISNS and GND pins.
  • Avoid connecting traces carrying large AC currents through a ground plane. Instead, use PCB traces on the top layer to conduct the AC current and use the ground plane as a noise shield.
  • Split the ground plane as necessary to keep noise away from the TPS40210-EP and noise sensitive areas such as components connected to the RC pin, FB pin, COMP pin and SS pin. Also keep these noise sensitive components close to the TPS40210-EP IC.
  • Keep C7 near the BP and GND pins to provide good bypass for the BP regulator.
  • The GDRV trace should be as close as possible to the power FET gate to minimize parisitic resistance and inductance in the trace. The parasitics should also be minimized in the return path from the source of the MOSFET, through the sense resistor and back to the GND pin.
  • Keep the SW node as physically small as possible to minimize parasitic capacitance and radiated emissions.
  • For good output voltage regulation, Kelvin connections should be brought from the load to the top FB resistor R7.

10.2 Layout Example

TPS40210-EP fig12_lus308.gif Figure 35. Component Placement
TPS40210-EP fig14_lus308.gif Figure 36. Top Copper
TPS40210-EP fig15_lus308.gif Figure 37. Bottom Copper Viewed from Top
TPS40210-EP fig16_lus308.gif Figure 38. Internal 1 Copper Viewed from Top
TPS40210-EP fig17_lus308.gif Figure 39. Internal 2 Copper Viewed from Top