SLUS772G March   2008  – June 2020 TPS40210 , TPS40211

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Soft Start
      2. 7.3.2  BP Regulator
      3. 7.3.3  Shutdown (DIS/ EN Pin)
      4. 7.3.4  Minimum On-Time and Off-Time Considerations
      5. 7.3.5  Setting the Oscillator Frequency
      6. 7.3.6  Synchronizing the Oscillator
      7. 7.3.7  Current Sense and Overcurrent
      8. 7.3.8  Current Sense and Subharmonic Instability
      9. 7.3.9  Current Sense Filtering
      10. 7.3.10 Control Loop Considerations
      11. 7.3.11 Gate Drive Circuit
      12. 7.3.12 TPS40211
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Near Minimum Input Voltage
      2. 7.4.2 Operation With DIS/ EN Pin
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 12-V to 24-V Nonsynchronous Boost Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design with WEBENCH Tools
          2. 8.2.1.2.2  Duty Cycle Estimation
          3. 8.2.1.2.3  Inductor Selection
          4. 8.2.1.2.4  Rectifier Diode Selection
          5. 8.2.1.2.5  Output Capacitor Selection
          6. 8.2.1.2.6  Input Capacitor Selection
          7. 8.2.1.2.7  Current Sense and Current Limit
          8. 8.2.1.2.8  Current Sense Filter
          9. 8.2.1.2.9  Switching MOSFET Selection
          10. 8.2.1.2.10 Feedback Divider Resistors
          11. 8.2.1.2.11 Error Amplifier Compensation
          12. 8.2.1.2.12 RC Oscillator
          13. 8.2.1.2.13 Soft-Start Capacitor
          14. 8.2.1.2.14 Regulator Bypass
          15. 8.2.1.2.15 Bill of Materials
        3. 8.2.1.3 Application Curves
      2. 8.2.2 12-V Input, 700-mA LED Driver, Up to 35-V LED String
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2.      65
      3. 11.1.2 Related Devices
      4. 11.1.3 Development Support
        1. 11.1.3.1 Custom Design with WEBENCH Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1.     78

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DRC|10
  • DGQ|10
Thermal pad, mechanical data (Package|Pins)
Orderable Information
8.2.1.2.9 Switching MOSFET Selection

The TPS40210 drives a ground referenced N-channel FET. The RDS(on) and gate charge are estimated based on the desired efficiency target.

Equation 53. GUID-76806A0C-B8FE-4563-8670-C8601CB9352F-low.gif

For a target of 95% efficiency with a 24-V input voltage at 2 A, maximum power dissipation is limited to 2.526 W. The main power dissipating devices are the MOSFET, inductor, diode, current sense resistor and the integrated circuit, the TPS40210.

Equation 54. GUID-43C10A01-CD48-489F-AE78-499C5D82AC37-low.gif

This leaves 812 mW of power dissipation for the MOSFET. This can likely cause an SO-8 MOSFET to get too hot, so power dissipation is limited to 500 mW. Allowing half for conduction and half for switching losses, we can determine a target RDS(on) and QGS for the MOSFET by Equation 55 and Equation 56.

Equation 55. GUID-EA07032E-DACD-4551-B24B-9570DABBF034-low.gif

A target MOSFET gate-to-source charge of less than 13.0 nC is calculated to limit the switching losses to less than 250 mW.

Equation 56. GUID-C72A28B9-B176-401F-8BCF-8FFD3543AFF0-low.gif

A target MOSFET RDS(on) of 9.9 mΩ is calculated to limit the conduction losses to less than 250 mW. Reviewing 30-V and 40-V MOSFETs, an Si4386DY 9-mΩ MOSFET is selected. A gate resistor was added per Equation 30. The maximum gate charge at VGS= 8V for the Si4386DY is 33.2 nC, this implies RG = 3.3 Ω.