SLUS772G March   2008  – June 2020 TPS40210 , TPS40211

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Soft Start
      2. 7.3.2  BP Regulator
      3. 7.3.3  Shutdown (DIS/ EN Pin)
      4. 7.3.4  Minimum On-Time and Off-Time Considerations
      5. 7.3.5  Setting the Oscillator Frequency
      6. 7.3.6  Synchronizing the Oscillator
      7. 7.3.7  Current Sense and Overcurrent
      8. 7.3.8  Current Sense and Subharmonic Instability
      9. 7.3.9  Current Sense Filtering
      10. 7.3.10 Control Loop Considerations
      11. 7.3.11 Gate Drive Circuit
      12. 7.3.12 TPS40211
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Near Minimum Input Voltage
      2. 7.4.2 Operation With DIS/ EN Pin
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 12-V to 24-V Nonsynchronous Boost Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design with WEBENCH Tools
          2. 8.2.1.2.2  Duty Cycle Estimation
          3. 8.2.1.2.3  Inductor Selection
          4. 8.2.1.2.4  Rectifier Diode Selection
          5. 8.2.1.2.5  Output Capacitor Selection
          6. 8.2.1.2.6  Input Capacitor Selection
          7. 8.2.1.2.7  Current Sense and Current Limit
          8. 8.2.1.2.8  Current Sense Filter
          9. 8.2.1.2.9  Switching MOSFET Selection
          10. 8.2.1.2.10 Feedback Divider Resistors
          11. 8.2.1.2.11 Error Amplifier Compensation
          12. 8.2.1.2.12 RC Oscillator
          13. 8.2.1.2.13 Soft-Start Capacitor
          14. 8.2.1.2.14 Regulator Bypass
          15. 8.2.1.2.15 Bill of Materials
        3. 8.2.1.3 Application Curves
      2. 8.2.2 12-V Input, 700-mA LED Driver, Up to 35-V LED String
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2.      65
      3. 11.1.2 Related Devices
      4. 11.1.3 Development Support
        1. 11.1.3.1 Custom Design with WEBENCH Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1.     78

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DRC|10
  • DGQ|10
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2 BP Regulator

The TPS40210 and TPS40211 have an on-board linear regulator that supplies power to the internal circuitry of the controller, including the gate driver. This regulator has a nominal output voltage of 8 V and must be bypassed with a 1-μF capacitor. If the voltage at the VDD pin is less than 8 V, the voltage on the BP pin will also be less and the gate drive voltage to the external FET is reduced from the nominal 8 V. This should be considered when choosing a FET for the converter.

Connecting external loads to this regulator can be done, but care must be taken to ensure that the thermal rating of the device is observed since there is no thermal shutdown feature in this controller. Exceeding the thermal ratings causes out of specification behavior and can lead to reduced reliability. The controller dissipates more power when there is an external load on the BP pin and is tested for dropout voltage for up to 5-mA load. When the controller is in the disabled state, the BP pin regulator also shuts off so loads connected there power down as well. When the controller is disabled with the DIS/ EN pin, this regulator is turned off.

The total power dissipation in the controller can be calculated as follows. The total power is the sum of PQ, PG, and PE.

Equation 7. GUID-F032C207-3684-4B1F-80B8-C2682FAA52A7-low.gif
Equation 8. GUID-C9EDD426-5952-440E-AD49-81C9809EEF9A-low.gif
Equation 9. GUID-5E021357-8948-45B1-B06A-2F616E77129B-low.gif

where

  • PQ is the quiescent power of the device in W
  • VDD is the VDD pin voltage in V
  • IDD(en) is the quiescent current of the controller when enabled but not switching in A
  • PG is the power dissipated by driving the gate of the FET in W
  • Qg is the total gate charge of the FET at the voltage on the BP pin in C
  • fSW is the switching frequency in Hz
  • PE is the dissipation caused be external loading of the BP pin in W
  • IEXT is the external load current in A