10.1.2 Layout Guidelines for Power Stage Device
Below are the PCB layout considerations for power stage. Please refer to the datasheet of the chosen power stage for more layout information.
- Input bypass capacitors should be as close as physically possible to the VIN and GND terminals of power stage. Additionally, a high-frequency bypass capacitor on the power stage VIN terminals can help to reduce switching ringing.
- Minimize the SW copper area for best noise performance. Route sensitive traces away from SW, as it contain fast switching voltage and lend easily to capacitive coupling.
- The bypass capacitors for VDD, REFIN and TAO pins must be placed as close to the power stage as possible.