SLUSBO6C JANUARY 2014 – October 2018 TPS40425
PRODUCTION DATA.
The EN_SPS bit in MFR_SPECIFIC_21 register is set to 0b in factory default. It must be set to 0b to allow TPS40425 to work at non-smart power mode.
The default value 20 V/V is recommended for CH1_CSGAIN_SEL and CH2_CSGAIN_SEL bits for most applications.
The en_adc_ctl bit is set to 1b in factory default to enable ADC operation such that the information of output voltage, output current and temperature can be provided by TPS40425 through PMBus.