SLUSBO6C JANUARY   2014  – October 2018 TPS40425

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1. 3.1 Simplified Application Diagram (Dual Output)
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Asynchronous Pulse Injection (API)
      2. 7.3.2  Adaptive Voltage Scaling (AVS)
      3. 7.3.3  Switching Frequency and Synchronization
      4. 7.3.4  Voltage Reference
      5. 7.3.5  Output Voltage and Remote Sensing Amplifier
      6. 7.3.6  Current Sensing and Temperature Sensing Modes
        1. 7.3.6.1 Non Smart-Power Operation
        2. 7.3.6.2 Smart-Power Operation.
      7. 7.3.7  Current Sensing
      8. 7.3.8  Temperature Sensing
      9. 7.3.9  Current Sharing
      10. 7.3.10 Linear Regulators
      11. 7.3.11 Power Sequence Between TPS40425 Device and Power Stage
      12. 7.3.12 PWM Signal
        1. 7.3.12.1 PWM Behavior During Soft-start Operation
      13. 7.3.13 Startup and Shutdown
      14. 7.3.14 Pre-Biased Output Start-up
      15. 7.3.15 PGOOD Indication
      16. 7.3.16 Overcurrent Protection
      17. 7.3.17 Overvoltage/Undervoltage Protection
      18. 7.3.18 Overtemperature Fault Protection
      19. 7.3.19 Input Undervoltage Lockout (UVLO)
      20. 7.3.20 Fault Communication
      21. 7.3.21 Fault Protection Summary
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Multi-Phase Applications
    6. 7.6 Register Maps
      1. 7.6.1 PMBus General Description
      2. 7.6.2 PMBus Functionality
        1. 7.6.2.1 PMBus Address
        2. 7.6.2.2 PMBus Connections
        3. 7.6.2.3 PMBus Data Format
        4. 7.6.2.4 PMBus Output Voltage Adjustment
          1. 7.6.2.4.1 No Margin Voltage
          2. 7.6.2.4.2 Margin High Voltage State
          3. 7.6.2.4.3 Margin Low State
      3. 7.6.3 Reading the Output Current
      4. 7.6.4 Soft-Start Time
      5. 7.6.5 Turn-On/Turn-Off Delay and Sequencing
    7. 7.7 Supported PMBus Commands
      1. 7.7.1  PAGE (00h)
      2. 7.7.2  OPERATION (01h)
      3. 7.7.3  ON_OFF_CONFIG (02h)
      4. 7.7.4  CLEAR_FAULTS (03h)
      5. 7.7.5  WRITE_PROTECT (10h)
      6. 7.7.6  STORE_USER_ALL (15h)
      7. 7.7.7  RESTORE_USER_ALL (16h)
      8. 7.7.8  CAPABILITY (19h)
      9. 7.7.9  VOUT_MODE (20h)
      10. 7.7.10 VIN_ON (35h)
      11. 7.7.11 VIN_OFF (36h)
      12. 7.7.12 IOUT_CAL_GAIN (38h)
      13. 7.7.13 IOUT_CAL_OFFSET (39h)
      14. 7.7.14 IOUT_OC_FAULT_LIMIT (46h)
      15. 7.7.15 IOUT_OC_FAULT_RESPONSE (47h)
      16. 7.7.16 IOUT_OC_WARN_LIMIT (4Ah)
      17. 7.7.17 OT_FAULT_LIMIT (4Fh)
      18. 7.7.18 OT_WARN_LIMIT (51h)
      19. 7.7.19 TON_RISE (61h)
      20. 7.7.20 STATUS_BYTE (78h)
      21. 7.7.21 STATUS_WORD (79h)
      22. 7.7.22 STATUS_VOUT (7Ah)
      23. 7.7.23 STATUS_IOUT (7Bh)
      24. 7.7.24 STATUS_TEMPERATURE (7Dh)
      25. 7.7.25 STATUS_CML (7Eh)
      26. 7.7.26 STATUS_MFR_SPECIFIC (80h)
      27. 7.7.27 READ_VOUT (8Bh)
      28. 7.7.28 READ_IOUT (8Ch)
      29. 7.7.29 READ_TEMPERATURE_2 (8Eh)
      30. 7.7.30 PMBus_REVISION (98h)
      31. 7.7.31 MFR_SPECIFIC_00 (D0h)
      32. 7.7.32 MFR_SPECIFIC_04 (VREF_TRIM) (D4h)
      33. 7.7.33 MFR_SPECIFIC_05 (STEP_VREF_MARGIN_HIGH) (D5h)
      34. 7.7.34 MFR_SPECIFIC_06 (STEP_VREF_MARGIN_LOW) (D6h)
      35. 7.7.35 MFR_SPECIFIC_07 (PCT_VOUT_FAULT_PG_LIMIT) (D7h)
      36. 7.7.36 MFR_SPECIFIC_08 (SEQUENCE_TON_TOFF_DELAY) (D8h)
      37. 7.7.37 MFR_SPECIFIC_16 (COMM_EEPROM_SPARE) (E0h)
      38. 7.7.38 MFR_SPECIFIC_21 (OPTIONS) (E5h)
      39. 7.7.39 MFR_SPECIFIC_22 (PWM_OSC_SELECT) (E6h)
      40. 7.7.40 MFR_SPECIFIC_23 (MASK SMBALERT) (E7h)
      41. 7.7.41 MFR_SPECIFIC_25 (AVS_CONFIG) (E9h)
      42. 7.7.42 MFR_SPECIFIC_26 (AVS_ADDRESS) (EAh)
      43. 7.7.43 MFR_SPECIFIC_27 (AVS_DAC_DEFAULT) (EBh)
      44. 7.7.44 MFR_SPECIFIC_28 (AVS_CLAMP_HI) (ECh)
      45. 7.7.45 MFR_SPECIFIC_29 (AVS_CLAMP_LO) (EDh)
      46. 7.7.46 MFR_SPECIFIC_30 (TEMP_OFFSET) (EEh)
      47. 7.7.47 MFR_SPECIFIC_32 (API_OPTIONS) (F0h)
      48. 7.7.48 MFR_SPECIFIC_44 (DEVICE_CODE) (FCh)
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Dual-Output Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Design Procedure
        1. 8.2.3.1  Switching Frequency Selection
        2. 8.2.3.2  Inductor Selection
        3. 8.2.3.3  Output Capacitor Selection
          1. 8.2.3.3.1 Output Voltage Deviation During Load Transient
          2. 8.2.3.3.2 Output Voltage Ripple
        4. 8.2.3.4  Input Capacitor Selection
        5. 8.2.3.5  VDD, BP5, BP3 Bypass Capacitor
        6. 8.2.3.6  R-C Snubber
        7. 8.2.3.7  Current and Temperature Sensor
        8. 8.2.3.8  Power Sequence Between the TPS40425 Device and Power Stage
        9. 8.2.3.9  Output Voltage Setting and Frequency Compensation Selection
        10. 8.2.3.10 Key PMBus Parameter Selection
          1. 8.2.3.10.1 MFR_SPECIFIC_21 (OPTIONS)
            1. 8.2.3.10.1.1 IOUT_CAL_GAIN
            2. 8.2.3.10.1.2 Enable and UVLO
            3. 8.2.3.10.1.3 Soft-Start Time
            4. 8.2.3.10.1.4 Overcurrent Threshold and Response
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout Guidelines for TPS40425 Device
      2. 10.1.2 Layout Guidelines for Power Stage Device
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Texas Instruments Fusion Digital Power Designer
        2. 11.1.1.2 TPS40k Loop Compensation Tool
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7.41 MFR_SPECIFIC_25 (AVS_CONFIG) (E9h)

Format Unsigned binary
Description This register is used for setting user selectable AVS configuration (AVS enable, double transmission check, payload size, and VREF slew-rate).
Default 0002h

The default power-up state can be changed using the STORE_USER commands.
PAGE0, PAGE1
r/wE r r r r r r r r r r/wE r/wE r/wE r/wE r/wE r/wE
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
AVS_EN AVS_IO AVS_STUP TX2 PAYLOAD<1:0> SLEW
Bits Field Name Description
7 AVS_EN (Format: binary)

Default: 0b

AVS mode enable

This bit, when high, enables the AVS mode of operation. Otherwise, the IC operates in the non-AVS mode. All other AVS commands (in effect, MFR_SPECIFIC_26, MFR_SPECIFIC_27, MFR_SPECIFIC_28, and MFR_SPECIFIC_29) are write-disabled (read-only access) in the AVS mode. An attempt to write to any of these registers in the AVS mode results in the “oth” bit in STATUS_CML to be set and SMBALERT to be declared. (MFR_SPECIFIC_27 has a slight exception here, as it is writeable in AVS_STARTUP mode). Also, the following PMBus commands related to VREF_TRIM and MARGIN are disabled (both read and write) and NACK’d in the AVS mode:

MFR_04 (D4h) VREF_TRIM

MFR_05 (D5h) STEP_VREF_MARGIN_HIGH

MFR_06 (D6h) STEP_VREF_MARGIN_LOW

To change this value, the user must change this value in the register, save it to the EEPROM and then reboot the device via power down for the new value to take effect.

0: PMBus mode enabled

1: AVS mode enabled
6:0

7:6		 Note: Any values written to read-only registers are ignored.
5 AVS_IO (Format: binary)
Default: 0b

AVS I/O adjust

This bit, when high, changes the internal logic level detection circuit (sensing the AVS_CLK and AVS_DATA signals at the IC pins) from 2.5 V to 1.8 V. This signal is only defined on PAGE 0 (channel 1). Since there is a single AVS interface to TPS40425, the setting here effectively applies to both channels. The corresponding bit on PAGE 1 is read-only and set to a default of 0.

0: AVS CLK and DATA signals from ASIC are at 2.5-V logic

1: AVS CLK and DATA signals from ASIC are at 1.8-V logic
4 AVS_STUP (Format: binary)
Default: 0b

AVS startup mode enable

This bit when high enables a mode called AVS_STARTUP mode, which is a sub-mode of the AVS mode. The AVS_STARTUP mode can only be enabled when the channel is in the AVS mode (in effect, it cannot be enabled in the non-AVS mode, even if the AVS_STUP bit is set high.). There are a few key features of the AVS_STARTUP mode:

MMMa. When in the AVS mode, the user can change to and from the AVS_STARTUP mode “on-the-fly” by simply changing the state of the AVS_STUP bit, without having to power-cycle the part

MMMb. When in the AVS_STARTUP mode, the reference voltage VREF is determined by the contents of MFR_27 (EBh). The slew rate of VREF is controlled by TON_RISE or AVS_SLEW, depending on what operating state the channel is in:
MMMMo While on SoftStart, Slew rate is controlled by TON_RISE.

MMMMo After SoftStart (this is Normal Operation), Slew rate is controlled by AVS_SLEW (MFR25[0]).

MMMc. When in the AVS_STARTUP mode, the user can change the contents of MFR_27 (EB) by PMBus to enable the control of the VREF by PMBus

MMMd. When in the AVS_STARTUP mode, all commands on the AVS bus are ignored.
3 TX2 (Format: binary)
Default: 0b

AVS Double Transmission Check Select

This bit is used to force the AVS slave to require any AVS command to be issued twice before it is acted upon.

0: Every commit-write actually takes effect as indicated by the AVS Master.

1: Every commit-write attempt must be performed twice for it to take effect.

This bit should not change while AVS is enabled.
2:1 PAYLOAD<1:0> (Format: binary)
Default: 01b

AVS Payload Configuration

This bit-field determines the number of bits that the device uses for sending “Voltage” in an AVS read frame, as well as the number of bits that the device expects in an AVS write frame. Considering that TPS40425’s encoding for the DAC voltage requires 10 bits, the setting for 8 bits is not acceptable .

00: 8-bit voltage – Reserved, not to be used in TPS40425.

01: 10-bit voltage, the minimum size (and the default setting).
10: 12-bit voltage. Allowed.

11: 16-bit voltage. Allowed.

This bit field should not change while AVS is enabled.
0 SLEW (Format: binary)
Default: 0b

AVS Slew rate select

This bit is used to select between fast (default) and slow AVS transition rates by adjusting the slew rate of the error-amplifier reference voltage VREF.

0: Fast AVS slew rate selected (200 mV / 30 µs)

1: Slow AVS rate selected (2 mV / 30 µs – slowest soft-start rate)

Table 15 summarizes the various mode transitions.

Table 15. Mode State Transitions

INITIAL MODE INPUT

CONDITIONS 		IF THIS EVENT

OCCURS		 FINAL

MODE
AVS_EN AVS_STUP
AVS X X No power-cycle AVS
AVS 1 0 Power cycle AVS
AVS 1 1 Power cycle AVS_STARTUP
AVS 0 X Power cycle PMBus
AVS X 1 No power cycle AVS_STARTUP
AVS_STARTUP X 1 No power cycle AVS_STARTUP
AVS_STARTUP 1 0 With or without power cycle AVS
AVS_STARTUP 1 1 Power cycle AVS_STARTUP
AVS_STARTUP 0 X Power cycle PMBus
PMBus X X No power cycle PMBus
PMBus 0 X Power cycle PMBus
PMBus 1 0 Power cycle AVS
PMBus 1 1 Power cycle AVS_STARTUP