SLUSBO6C JANUARY 2014 – October 2018 TPS40425
PRODUCTION DATA.
| Format | Unsigned binary | ||||
| Description | This paged register is used for setting user selectable lower limit for AVS reference DAC input for each channel. The LSB is 2 mV. An attempt to write a DAC input lower than this limit (from any source – explicit AVS command or AVS_DAC_DEFAULT) results in the actual DAC input being clamped to the setting in this register, and an ivd fault is declared with SMBALERT being triggered.
This command can only be written in the PMBus mode. In AVS or AVS_STARTUP mode, reads of this command are allowed, however - writes to this register (including from EEPROM during RESTORE_USER_ALL) are prevented in the AVS mode. An attempt to write to this register (not including RESTORE_USER_ALL) results in an ACK’d command, but the event results in the “oth” bit in STATUS_CML to be set and SMBALERT to be declared. |
||||
| Default | 00FAh
The default power-up state can be changed using the STORE_USER commands. |
||||
| PAGE0, PAGE1 | |||||||||||||||
| r | r | r | r | r | r | r/wE | r/wE | r/wE | r/wE | r/wE | r/wE | r/wE | r/wE | r/wE | r/wE |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AVS_CLAMP_LO<9:0> | |||||||||||||||
| Bits | Field Name | Description |
|---|---|---|
| 7:2 | Note: Any values written to read-only registers are ignored. | |
| 1:0
7:0 |
AVS_CLAMP_LO | (Format: binary)
Default: 0000 0000 1111 1010 b (250 decimal → 0.5 V) Maximum: 0000 0010 1110 1110 b (750 decimal → 1.5 V) Minimum: 0000 0000 1111 1010 b (250 decimal → 0.5 V) An attempt to write beyond the above set of limits results in an ivd fault, and triggering of SMBALERT. |