7.3.1.1 Frequency Selection and External Synchronization

The buck controllers operate using constant-frequency peak-current mode control for optimal transient behavior and ease of component choices. The switching frequency is programmable between 150 kHz and 600 kHz, depending upon the resistor value at the RT pin. A short circuit to ground at this pin sets the default switching frequency to 400 kHz. Using a resistor at RT, one can set another frequency according to Equation 1.

Equation 1.

For example:

• 600 kHz requires 40 kΩ
• 150 kHz requires 160 kΩ

It is also possible to synchronize to an external clock at the SYNC pin in the same frequency range of 150 kHz to 600 kHz. The device detects clock pulses at this pin, and an internal PLL locks on to the external clock within the specified range. The device can also detect a loss of clock at this pin, and on detection of this condition, the device sets the switching frequency to the internal oscillator. The two buck controllers operate at identical switching frequencies, 180 degrees out of phase.

7.3.1.2 Enable Inputs

Independent enable inputs from the ENA and ENB pins enable the buck controllers. These are high-voltage pins, with a threshold of 1.7 V for the high level, and with direct connection to the battery permissible for self-bias. The low threshold is 0.7 V. Both these pins have internal pullup currents of 0.5 µA (typical). As a result, an open circuit on these pins enables the respective buck controllers. But with both buck controllers disabled, the device shuts down and consumes a current less than 4 µA.

7.3.1.3 Feedback Inputs

The right resistor feedback divider network connected to the FBx (feedback) pins sets the output voltage. Choose this network such that the regulated voltage at the FBx pin equals 0.8 V. The FBx pins have a 100-nA pullup current source as a protection feature in case the pins open up as a result of physical damage.

7.3.1.4 Soft-Start Inputs

In order to avoid large inrush currents, the buck controllers have independent programmable soft-start timers. The voltage at the SSx pins acts as the soft-start reference voltage. The 1-µA pullup current available at the SSx pins, in combination with a suitably chosen capacitor, generates a ramp of the desired soft-start speed. After start-up, the pullup current ensures that this node is higher than the internal reference of 0.8 V, which then becomes the reference for the buck controllers. Use Equation 2 to calculate the soft-start ramp time..

Equation 2.

where

• I_SS = 1 µA (typical)
• ∆V = 0.8 V
• C_SS is the required capacitor for ∆t, the desired soft-start time.

An alternative use of the soft-start pins is as tracking inputs. In this case, connect them to the supply to be tracked via a suitable resistor-divider network.

7.3.1.5 Current-Mode Operation

Peak-current-mode control regulates the peak current through the inductor to maintain the output voltage at its set value. The error between the feedback voltage at FBx and the internal reference produces a signal at the output of the error amplifier (COMPx) which serves as a target for the peak inductor current. The device senses the current through the inductor as a differential voltage at Sx1–Sx2 and compares voltage with this target during each cycle. A fall or rise in load current produces a rise or fall in voltage at FBx, causing COMPx to fall or rise respectively, thus increasing or decreasing the current through the inductor until the average current matches the load. This process maintains the output voltage in regulation.

The top N-channel MOSFET turns on at the beginning of each clock cycle and stays on until the inductor current reaches its peak value. Once this MOSFET turns off, and after a small delay (shoot-through delay) the lower N-channel MOSFET turns on until the start of the next clock cycle. In dropout operation, the high-side MOSFET stays on continuously. In every fourth clock cycle, there is a limit on the duty cycle of 95% in order to charge the bootstrap capacitor at CBx. This allows a maximum duty cycle of 98.75% for the buck regulators. During dropout, the buck regulator switches at one-fourth of its normal frequency.

7.3.1.6 Current Sensing and Current Limit With Foldback

Clamping of the maximum value of COMPx is such as to limit the maximum current through the inductor to a specified value. When the output of the buck regulator (and hence the feedback value at FBx) falls to a low value due to a short-circuit or overcurrent condition, the clamped voltage at COMPx successively decreases, thus providing current foldback protection. This protects the high-side external MOSFET from excess current (forward-direction current limit).

Similarly, if a fault condition shorts the output to a high voltage and the low-side MOSFET turns fully on, the COMPx node drops low. A clamp is on its lower end as well, in order to limit the maximum current in the low-side MOSFET (reverse-direction current limit).

An external resistor senses the current through the inductor. Choose the sense resistor such that the maximum forward peak current in the inductor generates a voltage of 75 mV across the sense pins. This specified value is for low duty cycles only. At typical duty-cycle conditions around 40% (assuming 5-V output and 12-V input), 50 mV is a more reasonable value, considering tolerances and mismatches. The typical characteristics provide a guide for using the correct current-limit sense voltage.

The current-sense pins Sx1 and Sx2 are high-impedance pins with low leakage across the entire output range. This allows DCR current sensing using the dc resistance of the inductor for higher efficiency. Figure 11 shows DCR sensing. Here, the series resistance (DCR) of the inductor is the sense element. Place the filter components close to the device for noise immunity. Remember that while the DCR sensing gives high efficiency, it is inaccurate due to the temperature sensitivity and a wide variation of the parasitic inductor series resistance. Hence, it may often be advantageous to use the more-accurate sense resistor for current sensing.

Figure 11. DCR Sensing Configuration

7.3.1.7 Slope Compensation

Optimal slope compensation, which is adaptive to changes in input voltage and duty cycle, allows stable operation at all conditions. For optimal performance of this circuit, choose the inductor and sense resistor according to Equation 3.

Equation 3.

where

• L is the buck regulator inductor in henries.
• R_S is the sense resistor in ohms.
• f_sw is the buck-regulator switching frequency in hertz.

7.3.1.8 Power-Good Outputs and Filter Delays

Each buck controller has an independent power-good comparator monitoring the feedback voltage at the FBx pins and indicating whether the output voltage has fallen below a specified power-good threshold. This threshold has a typical value of 93% of the regulated output voltage. The power-good indicator is available as an open-drain output at the PGx pins. An internal 50-kΩ pullup resistor to Sx2 is available, or use of an external resistor is possible. Shutdown of a buck controller causes an internal pulldown of the power-good indicator. Connecting the pullup resistor to a rail other than the output of that particular buck channel causes a constant current flow through the resistor when the buck controller is in the powered-down state.

In order to avoid triggering the power-good indicators due to noise or fast transients on the output voltage, the device uses an internal delay circuit for de-glitching. Similarly, when the output voltage returns to its set value after a long negative transient, assertion of the power-good indicator (release of the open-drain pin) occurs after the same delay. Use of this delay can pauses the delay of the reset. Program the duration of the delay of by using a suitable capacitor at the DLYAB pin according to Equation 4.

Equation 4.

When the DLYAB pin is open, the delay setting is for a default value of 20 µs typical. The power-good delay timing is common to both the buck rails, but the power-good comparators and indicators function independently.

7.3.1.9 Light-Load PFM Mode

An external clock or a high level on the SYNC pin results in forced continuous-mode operation of the bucks. An open or low on the SYNC pin allows the buck controllers to operate in discontinuous mode at light loads by turning off the low-side MOSFET on detection of a zero-crossing in the inductor current.

In discontinuous mode, as the load decreases, the duration when both the high-side and low-side MOSFETs turn off increases (deep discontinuous mode). In case the duration exceeds 60% of the clock period and VBAT > 8 V, the buck controller switches to a low-power operation mode. The design ensures that this typically occurs at 1% of the set full-load current if the inductor and the sense resistor have been chosen appropriately as recommended in the Slope Compensation section.

In low-power PFM mode, the buck monitors the FBx voltage and compares it with the 0.8-V internal reference. Whenever the FBx value falls below the reference, the high-side MOSFET turns on for a pulse duration inversely proportional to the difference – Sx2. At the end of this on-time, the high-side MOSFET turns off and the current in the inductor decays until it becomes zero. The low-side MOSFET does not turn on. The next pulse occurs the next time FBx falls below the reference value. This results in a constant volt-second t_on hysteretic operation with a total device quiescent current consumption of 30 µA when a single buck channel is active and 35 µA when both channels are active.

As the load increases, the pulses become more and more frequent and move closer to each other until the current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed-frequency current-mode control. Another criterion to exit the low-power mode is when V_IN falls low enough to require higher than 80% duty cycle of the high-side MOSFET.

The TPS43350-Q1 and TPS43351-Q1 can support the full current load during low-power mode until the transition to normal mode takes place. The design ensures that exit of the low-power mode occurs at 10% (typical) of full-load current if the selection of inductor and sense resistor is as recommended. Moreover, there is always a hysteresis between the entry and exit thresholds to avoid oscillating between the two modes.

In the event that both buck controllers are active, low-power mode is only possible when both buck controllers have light loads that are low enough for low-power-mode entry.

Table 1. Frequency Hopping Control