SLVSAR7E June   2011  – October 2016 TPS43350-Q1 , TPS43351-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 Power Dissipation Derating Profile, 38-Pin HTTSOP PowerPAD Package
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Buck Controllers: Normal Mode PWM Operation
        1. 7.3.1.1 Frequency Selection and External Synchronization
        2. 7.3.1.2 Enable Inputs
        3. 7.3.1.3 Feedback Inputs
        4. 7.3.1.4 Soft-Start Inputs
        5. 7.3.1.5 Current-Mode Operation
        6. 7.3.1.6 Current Sensing and Current Limit With Foldback
        7. 7.3.1.7 Slope Compensation
        8. 7.3.1.8 Power-Good Outputs and Filter Delays
        9. 7.3.1.9 Light-Load PFM Mode
      2. 7.3.2 Frequency-Hopping Spread Spectrum (TPS43351-Q1 Only)
      3. 7.3.3 Gate-Driver Supply (VREG, EXTSUP)
      4. 7.3.4 External P-Channel Drive (GC2) and Reverse-Battery Protection
      5. 7.3.5 Undervoltage Lockout and Overvoltage Protection
      6. 7.3.6 Thermal Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  BuckA Component Selection
          1. 8.2.2.1.1 Minimum ON Time, tON min
          2. 8.2.2.1.2 Current-Sense Resistor RSENSE
        2. 8.2.2.2  Inductor Selection L
        3. 8.2.2.3  Inductor Ripple Current IRIPPLE
        4. 8.2.2.4  Output Capacitor COUTA
        5. 8.2.2.5  Bandwidth of Buck Converter fC
        6. 8.2.2.6  Selection of Components for Type II Compensation
        7. 8.2.2.7  Resistor Divider Selection for Setting VOUTA Voltage
        8. 8.2.2.8  BuckB Component Selection
        9. 8.2.2.9  Resistor Divider Selection for Setting VOUT Voltage
        10. 8.2.2.10 BUCKx High-Side and Low-Side N-Channel MOSFETs
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Buck Converter
      2. 10.1.2 Other Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DAP Package
38-Pin HTSSOP With PowerPAD
Top View

Pin Functions

NAME NO. TYPE DESCRIPTION
AGND 19, 23 GND Analog ground reference
CBA 5 I A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck controller BuckA. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
CBB 34 I A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck controller BuckB. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
COMPA 13 O Error amplifier output of BuckA and compensation node for voltage-loop stability. The voltage at this node sets the target for the peak current through the inductor of BuckA. Clamping his voltage on the upper and lower ends provides current-limit protection for the external MOSFETs.
COMPB 26 O Error amplifier output of BuckB and compensation node for voltage-loop stability. The voltage at this node sets the target for the peak current through the inductor of BuckB. Clamping his voltage on the upper and lower ends provides current-limit protection for the external MOSFETs.
DLYAB 21 O The capacitor at the DLYAB pin sets the power-good delay interval used to de-glitch the outputs of the power-good comparators. Leaving this pin open sets the power-good delay to an internal default value of 20 µs typical.
ENA 16 I Enable input for BuckA (active-high with an internal pullup current source). An input voltage higher than 1.7 V enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and ENB are low, the device shuts down and consumes less than 4 µA of current.
ENB 17 I Enable input for BuckB (active-high with an internal pullup current source). An input voltage higher than 1.7 V enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and ENB are low, the device shuts down and consumes less than 4 µA of current.
EXTSUP 37 I One can use EXTSUP to supply the VREG regulator from one of the TPS43350-Q1 or TPS43351-Q1 buck regulator rails to reduce power dissipation in cases where there is an expectation of high VIN. If EXTSUP is unused, leave the pin open without a capacitor installed.
FBA 12 I Feedback voltage pin for BuckA. The buck controller regulates the feedback voltage to the internal reference of 0.8 V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output voltage.
FBB 27 I Feedback voltage pin for BuckB. The buck controller regulates the feedback voltage to the internal reference of 0.8 V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output voltage.
GA1 6 O This output can drive the external high-side N-channel MOSFET for buck regulator BuckA. The output provides high peak currents to drive capacitive loads. The gate-drive reference is to a floating ground provided by PHA that has a voltage swing provided by CBA.
GA2 8 O This output can drive the external low-side N-channel MOSFET for buck regulator BuckA. The output provides high peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.
GB1 33 O This output can drive the external high-side N-channel MOSFET for buck regulator BuckB. The output provides high peak currents to drive capacitive loads. The gate drive reference is to a floating ground provided by PHB that has a voltage swing provided by CBB.
GB2 31 O This output can drive the external low-side N-channel MOSFET for buck regulator BuckB. The output provides high peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.
GC2 4 O This pin makes a floating output drive available to control the external P-channel MOSFET. This MOSFET can bypass the boost rectifier diode or a reverse-protection diode when the boost is not switching or if boost is disabled, and thus reduce power losses.
NC 2, 3, 18, 36 – No connection
PGNDA 9 GND Power ground connection to the source of the low-side N-channel MOSFETs of BuckA.
PGNDB 30 GND Power ground connection to the source of the low-side N-channel MOSFETs of BuckB
PGA 15 O Open-drain power-good indicator pin for BuckA. An internal power-good comparator monitors the voltage at the feedback pin and pulls this output low when the output voltage falls below 93% of the set value or if either VIN or VBAT drops below its respective undervoltage threshold.
PGB 24 O Open-drain power-good indicator pin for BuckB. An internal power-good comparator monitors the voltage at the feedback pin and pulls this output low when the output voltage falls below 93% of the set value or if either VIN or VBAT drops below its respective undervoltage threshold..
PHA 7 O Switching terminal of buck regulator BuckA, providing a floating ground reference for the high-side MOSFET gate-driver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired.
PHB 32 O Switching terminal of buck regulator BuckB, providing a floating ground reference for the high-side MOSFET gate-driver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired.
RT 22 O Connecting a resistor to ground on this pin sets the operational switching frequency of the buck and boost controllers. A short circuit to ground on this pin defaults operation to 400 kHz for the buck controllers and 200 kHz for the boost controller.
SA1 10 I High-impedance differential-voltage inputs from the current-sense element (sense resistor or inductor DCR) for each buck controller. Choose the current-sense element to set the maximum current through the inductor based on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle and VIN. (SA1 positive node, SA2 negative node).
SA2 11 I
SB1 29 I High-impedance differential voltage inputs from the current-sense element (sense resistor or inductor DCR) for each buck controller. Choose the current-sense element to set the maximum current through the inductor based on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle and VIN (SB1 positive node, SB2 negative node).
SB2 28 I
SSA 14 O Soft-start or tracking input for buck controller BuckA. The buck controller regulates the FBA voltage to the lower of 0.8 V or the SSA pin voltage.  An internal pullup current source of 1 µA is present at the pin, and an appropriate capacitor connected here sets the soft-start ramp interval. Alternatively, a resistor divider connected to another supply can provide a tracking input to this pin.
SSB 25 O Soft-start or tracking input for buck controller BuckB. The buck controller regulates the FBB voltage to the lower of 0.8 V or the SSB pin voltage.  An internal pullup current source of 1 µA is present at the pin, and an appropriate capacitor connected here sets the soft-start ramp interval. Alternatively, a resistor divider connected to another supply can provide a tracking input to this pin.
SYNC 20 I If an external clock is present on this pin, the device detects it, and the internal PLL locks on to the external clock. This overrides the internal oscillator frequency. The device can synchronize to frequencies from 150 kHz to 600 kHz. A high logic level on this pin ensures forced continuous-mode operation of the buck controllers and inhibits transition to low-power mode. An open or low allows discontinuous-mode operation and entry into low-power mode at light loads. On the TPS43351-Q1, a high level enables frequency-hopping spread spectrum, whereas an open or a low level disables it.
VBAT 1 PWR Supply pin
VIN 38 PWR Main input pin. This is the buck controller input pin. Additionally, it powers the internal control circuits of the device.
VREG 35 O The device requires an external capacitor on this pin to provide a regulated supply for the gate drivers of the buck and boost controllers. TI recommends capacitance on the order of 4.7 µF. The regulator obtain its power from either or EXTSUP. This pin has current-limit protection; do not use it to drive any other loads.
PowerPAD Pad GND PowerPAD thermal pad is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate, which is the ground of the device.