SLUSEZ1 December   2023 TPS4800-Q1

ADVANCE INFORMATION  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Charge Pump and Gate Driver Output (VS, PU, PD, BST, SRC)
      2. 7.3.2 Capacitive Load Driving Using FET Gate (PU, PD) Slew Rate Control
      3. 7.3.3 Short-Circuit Protection
        1. 7.3.3.1 Short-Circuit Protection With Auto-Retry
        2. 7.3.3.2 Short-Circuit Protection With Latch-Off
      4. 7.3.4 Overvoltage (OV) and Undervoltage Protection (UVLO)
      5. 7.3.5 Reverse Polarity Protection
      6. 7.3.6 Short-Circuit Protection Diagnosis (SCP_TEST)
      7. 7.3.7 TPS48000-Q1 as a Simple Gate Driver
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Application Limitations
        1. 8.1.1.1 Short-Circuit Protection Delay
        2. 8.1.1.2 Short-Circuit Protection Threshold
    2. 8.2 Typical Application: Driving Power at all Times (PAAT) Loads
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGX|19
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Design Procedure

Selection of MOSFET, Q1

For selecting the MOSFET Q1, important electrical parameters are the maximum continuous drain current ID, the maximum drain-to-source voltage VDS(MAX), the maximum drain-to-source voltage VGS(MAX), and the drain-to-source ON resistance RDSON.

The maximum continuous drain current, ID, rating must exceed the maximum continuous load current.

The maximum drain-to-source voltage, VDS(MAX), must be high enough to withstand the highest voltage seen in the application. Considering 60 V as the maximum application voltage due to load dump, MOSFETs with VDS voltage rating of 80 V is chosen for this application.

The maximum VGS TPS48000-Q1 can drive is 11 V, so a MOSFET with 15-V minimum VGS rating must be selected.

To reduce the MOSFET conduction losses, an appropriate RDS(ON) is preferred.

Based on the design requirements, IAUS200N08S5N023 is selected and its ratings are:

  • 80-V VDS(MAX) and ±20-V VGS(MAX)
  • RDS(ON) is 2.3-mΩ typical at 10-V VGS
  • MOSFET Qg(total) is 85-nC typical

TI recommends to make sure that the short-circuit conditions such max VIN and ISC are within SOA of selected FET (Q1) for at-least > tSC timing.

Selection of Bootstrap Capacitor, CBST

The internal charge pump charges the external bootstrap capacitor (connected between BST and SRC pins) with approximately 345 μA. Use the following equation to calculate the minimum required value of the bootstrap capacitor for driving IAUS200N08S5N023 MOSFET

Equation 10. C B S T   =   Q g ( t o t a l ) 1   V   =   85   n F  

Choose closest available standard value: 100 nF, 10%.

Programming the Short-Circuit Protection Threshold – RISCP Selection

The RISCP sets the short-circuit protection threshold, whose value can be calculated using below equation:

Equation 11. RISCP (Ω)= ISC×RDS_ON - 10 mV2 μA

Refer to Equation 9 in Section 8.1.1 section for update in equation in final revision of IC.

To set 60 A as short-circuit protection threshold, RISCP value is calculated to be 64 kΩ.

Choose the closest available standard value: 68 kΩ, 1%.

In case where large di/dt is involved, the system and layout parasitic inductances can generate large differential signal voltages between CS+ and CS– pins. This action can trigger false short-circuit protection and nuisance trips in the system. To overcome such scenario, TI suggests to add placeholder for RC filter components across sense resistor (RSNS) and tweak the values during test in the real system. The RC filter components should not be used in current sense designs by MOSFET VDS sensing to avoid impact on the short-circuit protection response.

Programming the Fault timer Period – CTMR Selection

For the design example under discussion, overcurrent transients are allowed for 50-μs duration. This blanking interval, tSC (or circuit breaker interval, TCB) can be set by selecting appropriate capacitor CTMR from TMR pin to ground. The value of CTMR to set 50 μs for tSC can be calculated using following equation:

Equation 12. CTMR=80 μA × tSC1.1

Choose closest available standard value: 3.3 nF, 10%.

Setting the Undervoltage Lockout and Overvoltage Set Point

The undervoltage lockout (UVLO) and overvoltage set point are adjusted using an external voltage divider network of R1, R2 and R3 connected between VS, EN/UVLO, OV and GND pins of the device. The values required for setting the undervoltage and overvoltage are calculated by solving Equation 13 and Equation 14.

Equation 13. GUID-20211208-SS0I-JNPH-FM8S-DSNZBH4V6RGS-low.svg
Equation 14. GUID-20211208-SS0I-CV3J-BJFK-CS8LWLDJRNDK-low.svg

For minimizing the input current drawn from the power supply, TI recommends to use higher values of resistance for R1, R2 and R3. However, leakage currents due to external active components connected to the resistor string can add error to these calculations. So, the resistor string current, I(R123) must be chosen to be 20 times greater than the leakage current of UVLO and OV pins.

From the device electrical specifications, V(OVR) = 1.24 V and V(UVLOR) = 1.24 V. From the design requirements, VINOVP is 60 V and VINUVLO is 16 V. To solve the equation, first choose the value of R1 = 470 kΩ and use Equation 13 to solve for (R2 + R3) = 39.5 kΩ. Use Equation 14 and value of (R2 + R3) to solve for R3 = 10.5 kΩ and finally R2 = 29 kΩ. Choose the closest standard 1% resistor values: R1 = 470 kΩ, R2 = 29.4 kΩ, and R3 = 10 kΩ.