SLUSEZ1 December   2023 TPS4800-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Charge Pump and Gate Driver Output (VS, PU, PD, BST, SRC)
      2. 7.3.2 Capacitive Load Driving Using FET Gate (PU, PD) Slew Rate Control
      3. 7.3.3 Short-Circuit Protection
        1. 7.3.3.1 Short-Circuit Protection With Auto-Retry
        2. 7.3.3.2 Short-Circuit Protection With Latch-Off
      4. 7.3.4 Overvoltage (OV) and Undervoltage Protection (UVLO)
      5. 7.3.5 Reverse Polarity Protection
      6. 7.3.6 Short-Circuit Protection Diagnosis (SCP_TEST)
      7. 7.3.7 TPS48000-Q1 as a Simple Gate Driver
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Application Limitations
        1. 8.1.1.1 Short-Circuit Protection Delay
        2. 8.1.1.2 Short-Circuit Protection Threshold
    2. 8.2 Typical Application: Driving Power at all Times (PAAT) Loads
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGX|19
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2 Capacitive Load Driving Using FET Gate (PU, PD) Slew Rate Control

Certain end equipments like automotive power distribution unit power different loads including other ECUs. These ECUs can have large input capacitances. If power to the ECUs is switched on in uncontrolled way, large inrush currents can occur potentially damaging the power FETs. To limit the inrush current during capacitive load switching, the following system design technique can be used with TPS48000-Q1.

For limiting inrush current during turn ON of the FET with capacitive loads, use R1, R2, C1 as shown in Figure 7-4. The R1 and C1 components slow down the voltage ramp rate at the gate of the FET. The FET source follows the gate voltage resulting in a controlled voltage ramp across the output capacitors.

GUID-20230517-SS0I-H1V5-WS2N-TNT4QFJN4NCH-low.svg Figure 7-4 Inrush Current limiting

Use the Equation 2 to calculate the inrush current during turn-ON of the FET.

Equation 2. IINRUSH= CLOAD× VBATTTcharge
Equation 3. C1= 0.63 × V(BST - SRC) × CLOADR1 × IINRUSH

Where,

CLOAD is the load capacitance,

VBATT is the input voltage and Tcharge is the charge time,

V(BST-SRC) is the charge pump voltage (11 V),

Use a damping resistor R2 (~ 10 Ω) in series with C1. Equation 3 can be used to compute required C1 value for a target inrush current. A 100 kΩ resistor for R1 can be a good starting point for calculations.

Connecting PD pin of TPS48000-Q1 directly to the gate of the external FET ensures fast turn OFF without any impact of R1 and C1 components.

C1 results in an additional loading on CBST to charge during turn-ON. Use below equation to calculate the required CBST value:

Equation 4. CBST = Qg(total)∆VBST+ 10 × C1

Where,

Qg(total) is the total gate charge of the FET.

ΔVBST (1 V typical) is the ripple voltage across BST to SRC pins.