Figure 7-1 shows a simplified diagram of the charge pump and gate driver circuit implementation. The device houses a strong 1.69-A/2-A peak source/sink gate driver (PU, PD) for driving power FET. The strong gate drivers enable paralleling of FETs in high power system designs ensuring minimum transition time in saturation region. A 11-V, 345-µA charge pump is derived from VS terminal and charges the external boot-strap capacitor, C_BST that is placed across the gate driver (BST and SRC).

VS is the supply pin to the controller. With VS applied and EN/UVLO pulled high, the charge pump turns ON and charges the C_BST capacitor. After the voltage across C_BST crosses V_{(BST_UVLOR)}, the GATE driver section is activated. The device has a 1-V (typical) UVLO hysteresis to ensure chattering less performance during initial GATE turn ON. Choose C_BST based on the external FET Q_G and allowed dip during FET turn-ON. The charge pump remains enabled until the BST to SRC voltage reaches 11.8 V, typically, at which point the charge pump is disabled decreasing the current draw on the VS pin. The charge pump remains disabled until the BST to SRC voltage discharges to 10 V typically at which point the charge pump is enabled. The voltage between BST and SRC continue to charge and discharge between 11.8 V and 10 V as shown in the Figure 7-2.

Figure 7-1 Gate Driver

Figure 7-2 Charge Pump Operation

Use the following equation to calculate the initial gate driver enable delay:

Where,

C_BST is the charge pump capacitance connected across BST and SRC pins.

V_{(BST_UVLOR)} = 9.5 V (max).

If T_{DRV_EN} must be reduced then pre-bias BST terminal externally using an external V_AUX supply through a low leakage diode D₁ as shown in Figure 7-3. With this connection, T_{DRV_EN} reduces to 400 µs. TPS48000-Q1 application circuit with external supply to BST is shown in Figure 7-3.

Figure 7-3 TPS48000-Q1 Application Circuit With External Supply to BST