SLUSEZ1 December   2023 TPS4800-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Charge Pump and Gate Driver Output (VS, PU, PD, BST, SRC)
      2. 7.3.2 Capacitive Load Driving Using FET Gate (PU, PD) Slew Rate Control
      3. 7.3.3 Short-Circuit Protection
        1. 7.3.3.1 Short-Circuit Protection With Auto-Retry
        2. 7.3.3.2 Short-Circuit Protection With Latch-Off
      4. 7.3.4 Overvoltage (OV) and Undervoltage Protection (UVLO)
      5. 7.3.5 Reverse Polarity Protection
      6. 7.3.6 Short-Circuit Protection Diagnosis (SCP_TEST)
      7. 7.3.7 TPS48000-Q1 as a Simple Gate Driver
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Application Limitations
        1. 8.1.1.1 Short-Circuit Protection Delay
        2. 8.1.1.2 Short-Circuit Protection Threshold
    2. 8.2 Typical Application: Driving Power at all Times (PAAT) Loads
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGX|19
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

GUID-20231106-SS0I-L1QD-PH20-M0KF4K7CCLJC-low.svg Figure 4-1 VSSOP19-Pin DGX Top View
Table 4-1 Pin Functions
PINTYPEDESCRIPTION
NAMETPS48000-Q1
DGX-19 (VSSOP)
EN/UVLO1I

EN/UVLO Input. A voltage on this pin above 1.24 V enables normal operation. Forcing this pin below 0.3 V shuts down the device reducing quiescent current to 1.5 µA (typical). Optionally connect to the input supply through a resistive divider to set the undervoltage lockout.

When EN/UVLO is left floating an internal pull down of 100 nA pulls EN/UVLO low and keeps the device in shutdown state.

OV

2I

Adjustable overvoltage threshold input. Connect a resistor ladder from input supply, OV to GND. When the voltage at OVP exceeds the overvoltage cut-off threshold then the PD is pulled down to SRC turning OFF the external FET. When the voltage at OV goes below OV falling threshold then PU gets pulled up to BST, turning ON the external FET.

OV must be connected to GND when not used. When OV is left floating an internal pull down of 100 nA pulls OV low and keeps PU pulled up to BST.

INP

3

I

Input Signal for external discharge FET control. CMOS compatible input reference to GND that sets the state of PD and PU pins.

INP has an internal weak pull down of 100 nA to GND to keep PD pulled to SRC when INP is left floating.

FLT_GD

4

O

Open Drain Fault Output for gate drive UVLO. This pin asserts low when gate drive across PU to SRC is above 7.5 V.
FLT

5

OOpen Drain Fault Output. This pin asserts low during short circuit fault, input UVLO and during SCP comparator diagnosis. If FLT feature is not desired then connect it to GND.
GND6GConnect GND to system ground.
CS_SEL7

I

Current sense select input. Connect this pin to ground to activate high side current sense. Drive this pin to > 2 V to activate low side current sensing.

CS_SEL has an internal weak pull down of 100 nA to GND.

ISCP8I

Short circuit detection setting. A resistor across ISCP to GND sets the short circuit current comparator threshold.

If short-circuit protection feature is not desired then connect CS+, CS–, VS pins together and connect ISCP, TMR pins to GND.

TMR9IFault Timer Input. A capacitor across TMR pin to GND sets the times for fault turn-off .
Leave it open for fastest setting.

If short-circuit protection feature is not desired then connect CS+, CS–, VS pins together and connect ISCP, TMR pins to GND.

SCP_TEST10I

Internal short circuit comparator (SCP) diagnosis input.

When SCP_TEST is driven low to high with INP pulled high, the internal SCP comparator’s operation is checked. FLT goes low and PD gets pulled to SRC if SCP comparator is functional.

Connect SCP_TEST pin to GND if this feature is not desired.

SCP_TEST has an internal weak pull down of 100 nA to GND.

N.C

11—

No connect

BST12OHigh Side Bootstrapped Supply. An external capacitor with a minimum value of > Qg(tot) of the external FET must be connected between this pin and SRC.
SRC13OSource connection of the external FET
PD14OHigh Current Gate Driver Pull-Down. This pin pulls down to SRC. For the fastest turn-off, tie this pin directly to the gate of the external high side MOSFET.
PU15OHigh Current Gate Driver Pull-Up. This pin pulls up to BST. Connect this pin to PD for maximum gate drive transition speed. A resistor can be connected between this pin and the gate of the external MOSFET to control the in-rush current during turn-on.
CS-17ICurrent sense negative input
CS+18ICurrent sense positive input.

N.C

19—

No connect

VS20PowerSupply pin of the controller