SLUSEW1 January   2024 TPS4810-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Charge Pump and Gate Driver Output (VS, G1PU, G1PD, G2, BST, SRC)
      2. 7.3.2 Capacitive Load Driving Using FET Gate (G1PU, G1PD) Slew Rate Control
      3. 7.3.3 Short-Circuit Protection
        1. 7.3.3.1 Short-Circuit Protection With Auto-Retry
        2. 7.3.3.2 Short-Circuit Protection With Latch-Off
      4. 7.3.4 Undervoltage Protection (UVLO)
      5. 7.3.5 Reverse Polarity Protection
      6. 7.3.6 Short-Circuit Protection Diagnosis (SCP_TEST)
      7. 7.3.7 TPS48100-Q1 as a Simple Gate Driver
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Application Limitations
        1. 8.1.1.1 Short-Circuit Protection Delay
        2. 8.1.1.2 Short-Circuit Protection Threshold
    2. 8.2 Typical Application: Circuit Breaker in Battery Management System (BMS) using Low Side Current Sense
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

TJ = –40 ℃ to +125℃. V(VS) = 48 V, V(BST – SRC) = 11 V, V(SRC) = 0 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
VS Operating input voltage 3.5 80 V
I(Q) Total system quiescent current, I(GND) V(EN/UVLO) = 2 V 35 µA
I(SHDN) SHDN current, I(GND) V(EN/UVLO) = 0 V, V(SRC) = 0 V 1.5 µA
ENABLE, UNDERVOLTAGE LOCKOUT (EN/UVLO), SHORT CIRCUIT COMPARATOR TEST (SCP_TEST) INPUT
V(UVLOR) UVLO threshold voltage, rising 1.24 V
V(UVLOF) UVLO threshold voltage, falling 1.14 V
V(ENR) Enable threshold voltage for low Iq shutdown, rising 1.02 V
V(ENF) Enable threshold voltage for low Iq shutdown, falling 0.3 V
V(SCP_TEST) SCP test mode rising threshold 1.02 V
V(SCP_TEST) SCP test mode rising threshold 0.3 V
I(EN/UVLO) Enable input leakage current V(EN/UVLO)  = 48 V 180 nA
CHARGE PUMP (BST–SRC)
V(BST – SRC_ON) Charge Pump turn on voltage V(EN/UVLO) = 2 V 10 V
V(BST – SRC_OFF) Charge Pump turn off voltage V(EN/UVLO) =  2 V 11.8 V
V(BST_UVLOR) V(BST – SRC) UVLO voltage threshold, rising V(EN/UVLO) = 2 V 9.5 V
V(BST_UVLOF) V(BST – SRC) UVLO voltage threshold, falling V(EN/UVLO) =  2 V 7.2 V
I(SRC) SRC pin leakage current V(EN/UVLO) =  2 V, V(INP1) = V(INP2) = 0 V 1 µA
GATE DRIVER OUTPUTS (G1PU, G1PD, G2)
I(G1PU) Peak Source Current 1.69 A
I(G2) G2 Peak Source Current 1.69 A
I(G1PD) Peak Sink Current 2 A
I(G2) G2 Peak Sink Current 2 A
V(G1_GOOD) VGS Good Threshold for G1 Gate Drive 7.5 V
SHORT CIRCUIT PROTECTION (ISCP)
V(SCP) SCP threshold  R(ISCP) =  145 kΩ 240 300 360 mV
R(ISCP) =  32.5 kΩ 75 mV
R(ISCP) =  15 kΩ 40 mV
DELAY TIMER (TMR)
I(TMR_SRC_CB) TMR source current 80 µA
I(TMR_SRC_FLT) TMR source current  2.2 µA
I(TMR_SNK) TMR sink current 2.5 µA
V(TMR_SC) 1.1 V
V(TMR_LOW) 0.2 V
N(A-R Count) 32
INPUT CONTROLS (INP1, INP2), CURRENT SENSE SELECT (CS_SEL) & FAULT FLAG (FLT)
R(FLT) FLT Pull-down resistance 70 Ω
V(INP1_H), V(INP2_H), V(CS_SEL_H)  2 V
V(INP1_L), V(INP2_L), V(CS_SEL_L)  0.8 V