SLUSFM1 December 2024 TPS4812-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Connect 100kΩ resistor across TMR pin to GND for latch-off configuration.
Latch is reset on falling edge of INP or LPM going low or EN/UVLO (below V(ENF)) or power cycle VS below V(VS_PORF). At low edge, the timer counter is reset and CTMR is discharged. GATE pulls up to BST when INP is pulled high.