SLUSFM1 December   2024 TPS4812-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Charge Pump and Gate Driver Output (VS, GATE, BST, SRC)
      2. 8.3.2 Capacitive Load Driving
        1. 8.3.2.1 Using Low-Power Bypass FET (G Drive) for Load Capacitor Charging
        2. 8.3.2.2 Using Main FET (GATE Drive) Gate Slew Rate Control
      3. 8.3.3 Overcurrent and Short-Circuit Protection
        1. 8.3.3.1 I2t-Based Overcurrent Protection
          1. 8.3.3.1.1 I2t-Based Overcurrent Protection With Auto-Retry
          2. 8.3.3.1.2 I2t-Based Overcurrent Protection With Latch-Off
        2. 8.3.3.2 Short-Circuit Protection
      4. 8.3.4 Analog Current Monitor Output (IMON)
      5. 8.3.5 NTC-Based Temperature Sensing (TMP) and Analog Monitor Output (ITMPO)
      6. 8.3.6 Fault Indication and Diagnosis (FLT)
      7. 8.3.7 Reverse Polarity Protection
      8. 8.3.8 Undervoltage Protection (UVLO)
    4. 8.4 Device Functional Modes
      1. 8.4.1 State Diagram
      2. 8.4.2 State Transition Timing Diagram
      3. 8.4.3 Power Down
      4. 8.4.4 Shutdown Mode
      5. 8.4.5 Low Power Mode (LPM)
      6. 8.4.6 Active Mode (AM)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application 1: Driving Power at all times (PAAT) Loads With Automatic Load Wakeup
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application 2: Driving Power at all times (PAAT) Loads With Automatic Load Wakeup and Output Bulk Capacitor Charging
      1. 9.3.1 Design Requirements
      2. 9.3.2 External Component Selection
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGE|23
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.5 Low Power Mode (LPM)

The device transitions from shutdown to low power mode when EN/UVLO is driven high ( >V(ENR)) and LPM is driven low for >500µs simultaneously.

The device can also transition from active mode to low power mode when LPM is pulled low. When entering from active mode to low power mode, LPM and INP signal sequencing consideration can be followed as per Figure 8-17. Pulling INP low before LPM results in main FET (GATE drive) turning OFF which can cause output voltage droop momentarily before bypass FET (G drive) turns ON. Pulling INP low after at least 10µs of LPM is pulled low makes a seamless transition from active to low power mode without any output voltage dip.

In this mode, charge pump and G gate drive are enabled. The main FET (GATE drive) is OFF and bypass FET (G drive) is turned ON and WAKE pin asserts high in this state. TPS4812-Q1 consumes low IQ of 20µA (typical) in low power mode.

The device transitions from low power mode to active mode when:

  • External Trigger: LPM is pulled high externally
  • Internal Trigger: Load current exceeds load wakeup trigger threshold (ILWU)

After load current exceeds load wakeup threshold (ILWU), the device automatically turns ON main FET (GATE drive) first and bypass FET (G drive) is turned OFF after main FET (GATE drive) has fully turned ON and WAKE asserts low indicating the exit from the low power mode.

The device waits for external LPM signal to go high to transition into Active mode.

Protections available in low power mode are:

  • Input UVLO: Bypass FET (G drive) is turned OFF when voltage on EN/UVLO falls below V(UVLOF).
  • Charge pump UVLO: Bypass FET (G drive) is turned OFF when voltage between BST to SRC falls below V(BST_UVLOF) and FLT asserts low.

  • Bypass FET Short-circuit Protection (Wakeup in short): This protection is available until VGS of bypass FET (G to SRC) reaches VG_GOOD threshold. If voltage across DRN and CS2– exceeds the set short-circuit threshold V(LPM_SCP) then, the device transitions to LOAD WAKEUP state by turning ON main FET (GATE drive) within tLPM_SC time.

    In LOAD WAKEUP state if load current is still high and exceeds set short-circuit threshold (VSCP) then, the device turns OFF main path (GATE drive) and bypass FET (G drive) within tSC time. The device goes in auto-retry or latch-off based on the selected configuration and FLT asserts low.