SLVSA94K December   2012  – May 2019 TPS50301-HT

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Efficiency vs Load Current, VIN = 5 V
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 8.3.2  PVIN vs Frequency
      3. 8.3.3  Voltage Reference
      4. 8.3.4  Adjusting the Output Voltage
      5. 8.3.5  Maximum Duty Cycle Limit
      6. 8.3.6  PVIN vs Frequency
      7. 8.3.7  Safe Start-Up into Prebiased Outputs
      8. 8.3.8  Error Amplifier
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Enable and Adjust UVLO
      11. 8.3.11 Adjustable Switching Frequency and Synchronization (SYNC)
      12. 8.3.12 Slow Start (SS/TR)
      13. 8.3.13 Power Good (PWRGD)
      14. 8.3.14 Bootstrap Voltage (BOOT) and Low Dropout Operation
      15. 8.3.15 Sequencing (SS/TR)
      16. 8.3.16 Output Overvoltage Protection (OVP)
      17. 8.3.17 Overcurrent Protection
        1. 8.3.17.1 High-Side MOSFET Overcurrent Protection
        2. 8.3.17.2 Low-Side MOSFET Overcurrent Protection
      18. 8.3.18 TPS50301-HT Thermal Shutdown
      19. 8.3.19 Turn-On Behavior
      20. 8.3.20 Small Signal Model for Loop Response
      21. 8.3.21 Simple Small Signal Model for Peak Current Mode Control
      22. 8.3.22 Small Signal Model for Frequency Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fixed-Frequency PWM Control
      2. 8.4.2 Continuous Current Mode (CCM) Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  Operating Frequency
        3. 9.2.2.3  Output Inductor Selection
        4. 9.2.2.4  Output Capacitor Selection
        5. 9.2.2.5  Input Capacitor Selection
        6. 9.2.2.6  Slow Start Capacitor Selection
        7. 9.2.2.7  Bootstrap Capacitor Selection
        8. 9.2.2.8  Undervoltage Lockout (UVLO) Set Point
        9. 9.2.2.9  Output Voltage Feedback Resistor Selection
          1. 9.2.2.9.1 Minimum Output Voltage
        10. 9.2.2.10 Compensation Component Selection
      3. 9.2.3 Parallel Operation
      4. 9.2.4 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Device Nomenclature

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

TJ = –55°C to 210°C, VIN = 3 to 6.3 V, PVIN = 1.6 to 6.3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN AND PVIN PINS)
PVIN operating input voltage 1.6 6.3 V
VIN operating input voltage 3 6.3 V
VIN internal UVLO threshold VIN rising 2.75 3 V
VIN internal UVLO hysteresis 50 mV
VIN shutdown supply current EN = 0 V 2.5 8 mA
VIN operating – non-switching supply current VSENSE = VBG 5 10 mA
ENABLE AND UVLO (EN PIN)
Enable threshold Rising 1.13 1.19 V
Enable threshold Falling 0.97 1.03 V
Input current VEN = 1.1 V 3.2 μA
Hysteresis current VEN = 1.3 V 3 μA
VOLTAGE REFERENCE
Voltage reference 0 A ≤ Iout ≤ 3 A –55°C 0.767 0.795 0.805 V
25°C 0.785 0.795 0.805
210°C 0.785 0.795 0.830
MOSFET
High-side switch resistance BOOT-PH = 2.2 V 55 mΩ
High-side switch resistance(1)(2) BOOT-PH = 6.3 V 50 mΩ
Low-side switch resistance(1)(2) VIN = 3 V 50 mΩ
ERROR AMPLIFIER
Error amplifier transconductance (gm)(2) –2 μA < ICOMP < 2 μA, V(COMP) = 1 V 1300 μS
Error amplifier dc gain(2) VSENSE = 0.8 V 39000 V/V
Error amplifier source/sink(2) V(COMP) = 1 V, 40 mV input overdrive ±125 μA
Start switching threshold(2) 0.25 V
COMP to Iswitch gm(2) 18 A/V
CURRENT LIMIT
High-side switch current limit threshold VIN = 6.3 V 7.8 11 A
Low-side switch sourcing current limit VIN = 6.3 V 6 10 A
Low-side switch sinking current limit VIN = 6.3 V 3 A
INTERNAL SWITCHING FREQUENCY
Internally set frequency RT = Open 395 500 585 kHz
Externally set frequency RT = 100 kΩ (1%) 480 kHz
RT = 485 kΩ (1%) 100
RT = 47 kΩ (1%) 1000
EXTERNAL SYNCHRONIZATION
SYNC out low-to-high rise time (10%/90%) Cload = 25 pF 25 126 ns
SYNC out high-to-low fall time (90%/10%) Cload = 25 pF 3 15 ns
Falling edge delay time(3) 180 °
SYNC out high-level threshold IOH = 50 µA 2 V
SYNC out low-level threshold IOL = 50 µA 600 mV
SYNC in low-level threshold 800 mV
SYNC in high-level threshold 1.85 V
SYNC in frequency range Percent of program frequency –5% 5%
100 1000 kHz
PH (PH PIN)
Minimum on time Measured at 10% to 90% of VIN,
25°C, IPH = 2 A		 94 236 ns
Minimum off time BOOT-PH ≥ 2.2 V 500 ns
BOOT (BOOT PIN)
BOOT-PH UVLO 2.2 3 V
SLOW START AND TRACKING (SS/TR PIN)
SS charge current 2.5 μA
SS/TR to VSENSE matching V(SS/TR) = 0.4 V 30 90 mV
POWER GOOD (PWRGD PIN)
VSENSE threshold VSENSE falling (fault) 91 % Vref
VSENSE rising (good) 94 % Vref
VSENSE rising (fault) 109 % Vref
VSENSE falling (good) 106 % Vref
Output high leakage VSENSE = Vref, V(PWRGD) = 5 V 0.03 2.9 µA
Output low I(PWRGD) = 2 mA 0.3 V
Minimum VIN for valid output V(PWRGD) < 0.5 V at 100 μA 0.6 1 V
Minimum SS/TR voltage for PWRGD 1.4 V
(1) Measured at pins
(2) Ensured by design only. Not tested in production.
(3) Bench verified. Not tested in production.