SLVSA94K December   2012  – May 2019 TPS50301-HT

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Efficiency vs Load Current, VIN = 5 V
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 8.3.2  PVIN vs Frequency
      3. 8.3.3  Voltage Reference
      4. 8.3.4  Adjusting the Output Voltage
      5. 8.3.5  Maximum Duty Cycle Limit
      6. 8.3.6  PVIN vs Frequency
      7. 8.3.7  Safe Start-Up into Prebiased Outputs
      8. 8.3.8  Error Amplifier
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Enable and Adjust UVLO
      11. 8.3.11 Adjustable Switching Frequency and Synchronization (SYNC)
      12. 8.3.12 Slow Start (SS/TR)
      13. 8.3.13 Power Good (PWRGD)
      14. 8.3.14 Bootstrap Voltage (BOOT) and Low Dropout Operation
      15. 8.3.15 Sequencing (SS/TR)
      16. 8.3.16 Output Overvoltage Protection (OVP)
      17. 8.3.17 Overcurrent Protection
        1. 8.3.17.1 High-Side MOSFET Overcurrent Protection
        2. 8.3.17.2 Low-Side MOSFET Overcurrent Protection
      18. 8.3.18 TPS50301-HT Thermal Shutdown
      19. 8.3.19 Turn-On Behavior
      20. 8.3.20 Small Signal Model for Loop Response
      21. 8.3.21 Simple Small Signal Model for Peak Current Mode Control
      22. 8.3.22 Small Signal Model for Frequency Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fixed-Frequency PWM Control
      2. 8.4.2 Continuous Current Mode (CCM) Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  Operating Frequency
        3. 9.2.2.3  Output Inductor Selection
        4. 9.2.2.4  Output Capacitor Selection
        5. 9.2.2.5  Input Capacitor Selection
        6. 9.2.2.6  Slow Start Capacitor Selection
        7. 9.2.2.7  Bootstrap Capacitor Selection
        8. 9.2.2.8  Undervoltage Lockout (UVLO) Set Point
        9. 9.2.2.9  Output Voltage Feedback Resistor Selection
          1. 9.2.2.9.1 Minimum Output Voltage
        10. 9.2.2.10 Compensation Component Selection
      3. 9.2.3 Parallel Operation
      4. 9.2.4 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Device Nomenclature

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.3 Parallel Operation

Configuring two TPS50601-SP in order to provide 12-A output current.

Design procedure is as follows - An example, Figure 30, shows parallel configuration using two TPS50601-SP in Master/Slave.

Important design steps are detailed as follows:

TPS50301-HT parallel_configuration_master_slave_slvsd45.gifFigure 30. Parallel Configuration Showing Master and Slave

For the master - RT pin must be left floating and this will set the frequency to 500 kHz.

In order to parallel two current mode control POLs (TPS50601-SP) one needs to do the following:

  1. RT pin on master must be left open (switching frequency 500-kHz typical (395-kHz minimum to 585-kHz maximum)) as highlighted in the data sheet frequency internally generated. For more details, see Adjustable Switching Frequency and Synchronization (SYNC) section.
    1. When RT pin is left open then sync pin becomes output.
  2. RT pin on slave should be selected within 5% of master ie RT = 96-kHz typical.
  3. Have a single feedback loop.
  4. Sync pins of master must be connected to sync pins of slave.
  5. Connect comp pins of two POLs together.
  6. Connect Vsense pins of two POLs together.
  7. Connect SS pins together.
  8. Connect enable pins together thus there is one enable.
TPS50301-HT parallel_configuration_extend_sync_slvsd45.gifFigure 31. Parallel Configuration With External Sync

Configuration when using an external clock is as follows: Refer to Figure 31.

  1. Master/slave configuration can also be achieved if desired using external clock ie if operating at 100 kHZ or any other customer selected frequency.
    1. External user supplied clock signal is required.
    2. RT pins of both master and slave must be populated with appropriate resistor value ie 475 kΩ (for 100 kHZ).
    3. Slave signal feeding the sync pin must be inverter.
  2. RT pin on both master and slave must be populated for 100 kHz operation RT = 495 kΩ.
  3. External user supplied clock signal is required.
  4. Connect comp pins of two POLs together.
  5. Connect Vsense pins of two POLs together.
  6. Connect SS pins together.
  7. Connect enable pins together thus there is one enable.