SLVSA94K December   2012  – May 2019 TPS50301-HT

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Efficiency vs Load Current, VIN = 5 V
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 8.3.2  PVIN vs Frequency
      3. 8.3.3  Voltage Reference
      4. 8.3.4  Adjusting the Output Voltage
      5. 8.3.5  Maximum Duty Cycle Limit
      6. 8.3.6  PVIN vs Frequency
      7. 8.3.7  Safe Start-Up into Prebiased Outputs
      8. 8.3.8  Error Amplifier
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Enable and Adjust UVLO
      11. 8.3.11 Adjustable Switching Frequency and Synchronization (SYNC)
      12. 8.3.12 Slow Start (SS/TR)
      13. 8.3.13 Power Good (PWRGD)
      14. 8.3.14 Bootstrap Voltage (BOOT) and Low Dropout Operation
      15. 8.3.15 Sequencing (SS/TR)
      16. 8.3.16 Output Overvoltage Protection (OVP)
      17. 8.3.17 Overcurrent Protection
        1. 8.3.17.1 High-Side MOSFET Overcurrent Protection
        2. 8.3.17.2 Low-Side MOSFET Overcurrent Protection
      18. 8.3.18 TPS50301-HT Thermal Shutdown
      19. 8.3.19 Turn-On Behavior
      20. 8.3.20 Small Signal Model for Loop Response
      21. 8.3.21 Simple Small Signal Model for Peak Current Mode Control
      22. 8.3.22 Small Signal Model for Frequency Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fixed-Frequency PWM Control
      2. 8.4.2 Continuous Current Mode (CCM) Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  Operating Frequency
        3. 9.2.2.3  Output Inductor Selection
        4. 9.2.2.4  Output Capacitor Selection
        5. 9.2.2.5  Input Capacitor Selection
        6. 9.2.2.6  Slow Start Capacitor Selection
        7. 9.2.2.7  Bootstrap Capacitor Selection
        8. 9.2.2.8  Undervoltage Lockout (UVLO) Set Point
        9. 9.2.2.9  Output Voltage Feedback Resistor Selection
          1. 9.2.2.9.1 Minimum Output Voltage
        10. 9.2.2.10 Compensation Component Selection
      3. 9.2.3 Parallel Operation
      4. 9.2.4 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Device Nomenclature

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.21 Simple Small Signal Model for Peak Current Mode Control

Figure 26 is a simple small signal model that can be used to understand how to design the frequency compensation. The device power stage can be approximated to a voltage-controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. Equation 13 shows the control to output transfer function, which consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 25) is the power stage transconductance (gmps), which is 18 A/V for the device. The dc gain of the power stage is the product of gmps and the load resistance (RL) as shown in Equation 14 with resistive loads. As the load current increases, the dc gain decreases. This variation with load may seem problematic at first glance, but fortunately, the dominant pole moves with load current (see Equation 15). The combined effect is highlighted by the dashed line in Figure 27. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions, which makes it easier to design the frequency compensation.

TPS50301-HT peak_cur_lvs949.gifFigure 26. Simplified Small Signal Model for Peak Current Mode Control
TPS50301-HT f_res_lvs949.gifFigure 27. Simplified Frequency Response for Peak Current Mode Control
Equation 13. TPS50301-HT eq8_vout_lvs949.gif
Equation 14. TPS50301-HT eq9_adc_lvs949.gif
Equation 15. TPS50301-HT eq10_fp_lvs949.gif
Equation 16. TPS50301-HT eq11_fz_lvs949.gif

where

  • gmea is the GM amplifier gain (1300 μA/V).
  • gmps is the power stage gain (18 A/V).
  • RL is the load resistance.
  • CO is the output capacitance.
  • RESR is the equivalent series resistance of the output capacitor.