SLVSDF5D September   2017  – October 2019 TPS50601A-SP

PRODUCTION DATA.  

  1. 1 Features
    1.     Efficiency at VIN = PVIN = 5 V
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 7.3.2  Voltage Reference
      3. 7.3.3  Adjusting the Output Voltage
      4. 7.3.4  Safe Start-Up Into Prebiased Outputs
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Slope Compensation
      7. 7.3.7  Enable and Adjust UVLO
      8. 7.3.8  Adjustable Switching Frequency and Synchronization (SYNC)
      9. 7.3.9  Slow Start (SS/TR)
      10. 7.3.10 Power Good (PWRGD)
      11. 7.3.11 Sequencing (SS/TR)
      12. 7.3.12 Output Overvoltage Protection (OVP)
      13. 7.3.13 Overcurrent Protection
        1. 7.3.13.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.13.2 Low-Side MOSFET Overcurrent Protection
      14. 7.3.14 Thermal Shutdown
      15. 7.3.15 Turn-On Behavior
      16. 7.3.16 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fixed-Frequency PWM Control
      2. 7.4.2 Continuous Current Mode (CCM) Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Operating Frequency
        2. 8.2.2.2 Output Inductor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Slow Start Capacitor Selection
        5. 8.2.2.5 Undervoltage Lockout (UVLO) Set Point
        6. 8.2.2.6 Output Voltage Feedback Resistor Selection
        7. 8.2.2.7 Compensation Component Selection
      3. 8.2.3 Parallel Operation
      4. 8.2.4 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TJ = –55°C to 125°C, VIN = PVIN = 3.0 V to 7.0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply Voltage (VIN AND PVIN Pins)
PVIN operating input voltage 3 7 V
PVIN internal UVLO threshold PVIN rising 2.50 V
PVIN internal UVLO hysteresis 450 mV
VIN operating input voltage 3 7 V
VIN internal UVLO threshold VIN rising 2.75 3 V
VIN internal UVLO hysteresis 150 mV
VIN shutdown supply current VEN = 0 V 1.35 2.5 mA
VIN operating – non switching supply current VSENSE = VBG 5 10 mA
Enable and UVLO (EN Pin)
Enable threshold Rising 1.14 1.18 V
Falling 1.05 1.11
Input current VEN = 1.1 V 6.1 μA
Hysteresis current VEN = 1.3 V 3 μA
Voltage Reference
Voltage reference 0 A ≤ Iout ≤ 6 A, –55 to 125°C 0.792 0.804 0.816 V
REFCAP voltage 470 nF 1.211 V
Mosfet
High-side switch resistance PVIN = VIN = 3 V, lead length = 4 mm 50 mΩ
High-side switch resistance(1) PVIN = VIN = 5 V, lead length = 4 mm 45 mΩ
High-side switch resistance(1) PVIN = VIN = 7 V, lead length = 4 mm 43 mΩ
Low-side switch resistance(1) PVIN = VIN= 3 V, lead length = 4 mm 35 mΩ
Low-side switch resistance(1) PVIN = VIN = 5 V, lead length = 4 mm 34 mΩ
Low-side switch resistance(1) PVIN = VIN = 7 V, lead length = 4 mm 33 mΩ
Error Amplifier
Error amplifier transconductance (gm)(2) –2 μA < ICOMP < 2 μA, V(COMP) = 1 V 1000 1400 2000 μS
Error amplifier dc gain(2) VSENSE = 0.804 V 10000 V/V
Error amplifier source/sink(2) V(COMP) = 1 V, 100-mV input overdrive –250 ±115 250 μA
Error amplifier output resistance 7 MΩ
Start switching threshold(2) 0.25 V
COMP to Iswitch gm(2) 22 S
Current Limit
High-side switch current limit threshold (3) VIN = 7 V 11 A
Low-side switch sourcing current limit(3) VIN = 7 V 10 A
Low-side switch sinking current limit VIN = 7 V 3 A
Thermal Shutdown
Thermal shutdown 170 °C
Thermal shutdown hysteresis 30 °C
Internal Switching Frequency
Internally set frequency RT = Open 395 500 585 kHz
Externally set frequency RT = 100 kΩ (1%) 395 500 585 kHz
RT = 487 kΩ (1%) 85 100 120
RT = 47 kΩ (1%) 900 1000 1100
External Synchronization
SYNC out low-to-high rise time (10%/90%) CLOAD = 25 pF 70 111 ns
SYNC out high-to-low fall time (90%/10%) CLOAD = 25 pF 6 15.5 ns
Falling edge delay time(5) 180 °
SYNC out high level threshold IOH = 50 µA VIN - 0.3 V
SYNC out low level threshold IOL = 50 µA 600 mV
SYNC in low level threshold PVIN = VIN = 3 V 900 mV
SYNC in high level threshold PVIN = VIN = 3 V 2.45 V
SYNC in low level threshold PVIN = VIN = 7 V 900 mV
SYNC in high level threshold PVIN = VIN = 7 V 4.25 V
SYNC in frequency range(4) 100 1000 kHz
PH (PH Pin)
Minimum on time Measured at 10% to 90% of VIN,
25°C, IPH = 2 A		 190 235 ns
Slow Start and Tracking (SS/TR Pin)
SS charge current 1.5 2.5 3 μA
SS/TR to VSENSE matching V(SS/TR) = 0.4 V 30 90 mV
Power Good (PWRGD Pin)
VSENSE threshold VSENSE falling (fault) 91 % VREF
VSENSE rising (good) 94
VSENSE rising (fault) 109
VSENSE falling (good) 106
Output high leakage VSENSE = VREF, V(PWRGD) = 5 V 30 181 nA
Output low I(PWRGD) = 2 mA 0.3 V
Minimum VIN for valid output V(PWRGD) < 0.5 V at 100 μA 0.6 1 V
Minimum SS/TR voltage for PWRGD 1.55 V
(1) Measured at pins.
(2) Ensured by design only. Not tested in production.
(3) Parameter is not tested in production.
(4) Parameter is production tested at nominal voltage with VIN = PVIN = 5 V.
(5) Bench verified. Not tested in production.