7.3.1 PWM Operations

The main control loop of the switch mode power supply (SMPS) is designed as an adaptive on-time pulse width modulation (PWM) controller. It supports a proprietary D-CAP mode. D-CAP mode does not require external compensation circuit and is suitable for low external component count configuration when used with appropriate amount of ESR at the output capacitor(s).

At the beginning of each cycle, the synchronous top MOSFET is turned on, or becomes ON state. This MOSFET is turned off, or becomes OFF state, after internal one-shot timer expires. This one shot is determined by V_IN and V_OUT to keep frequency fairly constant over input voltage range, hence it is called adaptive on-time control. The MOSFET is turned on again when the feedback point voltage, VFB, decreased to match with internal 2-V reference. The inductor current information is also monitored and should be below the overcurrent threshold to initiate this new cycle. Repeating operation in this manner, the controller regulates the output voltage. The synchronous bottom or the “rectifying” MOSFET is turned on at the beginning of each OFF state to keep the conduction loss minimum.The rectifying MOSFET is turned off before the top MOSFET turns on at next switching cycle or when inductor current information detects zero level. In the auto-skip mode or the OOA skip mode, this enables seamless transition to the reduced frequency operation at light load condition so that high efficiency is kept over broad range of load current.

7.3.2 Adaptive On-Time Control and PWM Frequency

TPS51125 does not have a dedicated oscillator onboard. However, the part runs with pseudo-constant frequency by feed-forwarding the input and output voltage into the on-time, one-shot timer. The on-time is controlled inverse proportional to the input voltage and proportional to the output voltage so that the duty ratio will be kept as VOUT/VIN technically with the same cycle time. The frequencies are set by TONSEL terminal connection as Table 1.

7.3.3 Loop Compensation

From small-signal loop analysis, a buck converter using D-CAP^TM mode can be simplified as shown in Figure 31.

Figure 31. Simplifying the Modulator

The output voltage is compared with internal reference voltage after divider resistors, R1 and R2. The PWM comparator determines the timing to turn on high-side MOSFET. The gain and speed of the comparator is high enough to keep the voltage at the beginning of each on cycle substantially constant. For the loop stability, the 0dB frequency, f₀, defined below need to be lower than 1/4 of the switching frequency.

Equation 1.

As f₀ is determined solely by the characteristics of the output capacitor, loop stability of D-CAP mode is determined by the chemistry of the capacitor. For example, specialty polymer capacitors (SP-CAP) have Co in the order of several 100 μF and ESR in range of 10 mΩ. These will make f₀ in the order of 100 kHz or less and the loop will be stable. However, ceramic capacitors have f₀ at more than 700 kHz, which is not suitable for this operational mode.

7.3.4 Ramp Signal

The TPS51125 adds a ramp signal to the 2-V reference in order to improve its jitter performance. As described in the previous section, the feedback voltage is compared with the reference information to keep the output voltage in regulation. By adding a small ramp signal to the reference, the S/N ratio at the onset of a new switching cycle is improved. Therefore the operation becomes less jitter and stable. The ramp signal is controlled to start with –20 mV at the beginning of ON-cycle and to become 0 mV at the end of OFF-cycle in steady state. By using this scheme, the TPS51125 improve jitter performance without sacrificing the reference accuracy.

7.3.5 Light-Load Condition in Auto-Skip Operation

The TPS51125 automatically reduces switching frequency at light-load conditions to maintain high efficiency. This reduction of frequency is achieved smoothly and without increase of V_OUT ripple. Detail operation is described as follows. As the output current decreases from heavy load condition, the inductor current is also reduced and eventually comes to the point that its ‘valley’ touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when this zero inductor current is detected. As the load current further decreased, the converter runs in discontinuous conduction mode and it takes longer and longer to discharge the output capacitor to the level that requires next ON cycle. The ON time is kept the same as that in the heavy load condition. In reverse, when the output current increase from light load to heavy load, switching frequency increases to the preset value as the inductor current reaches to the continuous conduction. The transition load point to the light load operation I_OUT(LL) (that is, the threshold between continuous and discontinuous conduction mode) can be calculated as follows;

Equation 2.

where

• f is the PWM switching frequency

Switching frequency versus output current in the light load condition is a function of L, V_IN and V_OUT, but it decreases almost proportional to the output current from the I_OUT(LL) given above. For example, it will be 60 kHz at I_OUT(LL)/5 if the frequency setting is 300 kHz.

7.3.6 Out-of-Audio Light-Load Operation

Out-of-Audio (OOA) light-load mode is a unique control feature that keeps the switching frequency above acoustic audible frequencies toward virtually no load condition while maintaining best of the art high conversion efficiency. When the Out-of-Audio operation is selected, OOA control circuit monitors the states of both MOSFET and force to change into the ON state if both of MOSFETs are off for more than 32 μs. This means that the top MOSFET is turned on even if the output voltage is higher than the target value so that the output capacitor is tends to be overcharged.

The OOA control circuit detects the over-voltage condition and begins to modulate the on time to keep the output voltage regulated. As a result, the output voltage becomes 0.5% higher than normal light-load operation.

7.3.7 VREG5/VREG3 Linear Regulators

There are two sets of 100-mA standby linear regulators which outputs 5 V and 3.3 V, respectively. The VREG5 serves as the main power supply for the analog circuitry of the device and provides the current for gate drivers. The VREG3 is intended mainly for auxiliary 3.3-V supply for the notebook system during standby mode.

Add a ceramic capacitor with a value of at least 33 μF and place it close to the VREG5 pin, and add at most 10 μF to the VREG3 pin. Total capacitance connected to the VREG3 pin should not exceed 10 μF.

7.3.8 VREG5 Switch Over

When the VO1 voltage becomes higher than 4.7 V AND channel-1 internal powergood flag is generated, internal 5-V LDO regulator is shut off and the VREG5 output is connected to VO1 by internal switch over MOSFET. The 510-μs powergood delay helps a switch over without glitch.

7.3.9 VREG3 Switch Over

When the VO2 voltage becomes higher than 3.15 V AND channel-2 internal powergood flag is generated, internal 3.3-V LDO regulator is shut off and the VREG3 output is connected to VO2 by internal switch over MOSFET. The 510-μs powergood delay helps a switch over without glitch.

7.3.10 Powergood

The TPS51125 has one powergood output that indicates 'high' when both switcher outputs are within the targets (AND gated). The powergood function is activated with 2-ms internal delay after ENTRIPx goes high. If the output voltage becomes within +/-5% of the target value, internal comparators detect power good state and the powergood signal becomes high after 510-μs internal delay. Therefore PGOOD goes high around 2.5 ms after ENTRIPx goes high. If the output voltage goes outside of +/-10% of the target value, the powergood signal becomes low after 2-μs internal delay. The powergood output is an open-drain output and is needed to be pulled up outside.

Also note that, in the case of Auto-skip or Out-of-Audio™ mode, if the output voltage goes +10% above the target value and the power-good signal flags low, then the loop attempts to correct the output by turning on the low-side driver (forced PWM mode). After the feedback voltage returns to be within +5% of the target value and the power-good signal goes high, the controller returns back to auto-skip mode or Out-of-Audio mode.

7.3.11 Output Discharge Control

When ENTRIPx is low, the TPS51125 discharges outputs using internal MOSFET which is connected to VOx and GND. The current capability of these MOSFETs is limited to discharge slowly.

7.3.12 Low-Side Driver

The low-side driver is designed to drive high current low R_DS(on) N-channel MOSFETs. The drive capability is represented by its internal resistance, which are 4 Ω for VREG5 to DRVLx and 1.5 Ω for DRVLx to GND. A dead time to prevent shoot through is internally generated between top MOSFET off to bottom MOSFET on, and bottom MOSFET off to top MOSFET on. 5-V bias voltage is delivered from VREG5 supply. The instantaneous drive current is supplied by an input capacitor connected between VREG5 and GND. The average drive current is equal to the gate charge at Vgs = 5 V times switching frequency. This gate drive current as well as the high-side gate drive current times 5 V makes the driving power which need to be dissipated from TPS51125 package.

7.3.13 High-Side Driver

The high-side driver is designed to drive high current, low R_DS(on) N-channel MOSFETs. When configured as a floating driver, 5-V bias voltage is delivered from VREG5 supply. The average drive current is also calculated by the gate charge at Vgs = 5 V times switching frequency. The instantaneous drive current is supplied by the flying capacitor between VBSTx and LLx pins. The drive capability is represented by its internal resistance, which are 4 Ω for VBSTx to DRVHx and 1.5Ω for DRVHx to LLx.

7.3.14 VCLK for Charge Pump

270-kHz clock signal can be used for charge pump circuit to generate approximately 15-V dc voltage. The clock signal becomes available when EN0 becomes higher than 2.4 V or open state. Example of control circuit is shown in Figure 32. Note that the clock driver uses VO1 as its power supply. Regardless of enable or disable of VCLK, power consumption of the TPS51125 is almost the same. Therefore even if VCLK is not used, one can let EN0 pin open or supply logic ‘high’, as shown in Figure 32, and let VCLK pin open. This approach further reduces the external part count.

Figure 32. Control Example of EN0 Master Enable

Figure 33. 15-V / 10-mA Charge Pump Configuration

7.3.15 Current Protection

TPS51125 has cycle-by-cycle over current limiting control. The inductor current is monitored during the OFF state and the controller keeps the OFF state during the inductor current is larger than the over current trip level. In order to provide both good accuracy and cost effective solution, TPS51125 supports temperature compensated MOSFET R_DS(on) sensing. ENTRIPx pin should be connected to GND through the trip voltage setting resistor, R_TRIP. ENTRIPx terminal sources I_TRIP current, which is 10 μA typically at room temperature, and the trip level is set to the OCL trip voltage V_TRIP as below. Note that the V_TRIP is limited up to about 205 mV internally.

Equation 3.

External leakage current to ENTRIPx pin should be minimized to obtain accurate OCL trip voltage.

The inductor current is monitored by the voltage between GND pin and LLx pin so that LLx pin should be connected to the drain terminal of the bottom MOSFET properly. Itrip has 4500 ppm/°C temperature slope to compensate the temperature dependency of the R_DS(on). GND is used as the positive current sensing node so that GND should be connected to the proper current sensing device, i.e. the source terminal of the bottom MOSFET.

As the comparison is done during the OFF state, V_TRIP sets valley level of the inductor current. Thus, the load current at over current threshold, I_OCP, can be calculated in Equation 4.

Equation 4.

In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output voltage tends to fall down. Eventually, it ends up with crossing the under voltage protection threshold and shutdown both channels.

7.3.16 Overvoltage and Undervoltage Protection

TPS51125 monitors a resistor divided feedback voltage to detect over and undervoltage. When the feedback voltage becomes higher than 115% of the target voltage, the OVP comparator output goes high and the circuit latches as the top MOSFET driver OFF and the bottom MOSFET driver ON.

Also, TPS51125 monitors VOx voltage directly and if it becomes greater than 5.75 V the TPS51125 turns off the top MOSFET driver.

When the feedback voltage becomes lower than 60% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins counting. After 32 μs, TPS51125 latches OFF both top and bottom MOSFETs drivers, and shut off both drivers of another channel. This function is enabled after 2 ms following ENTRIPx has become high.

7.3.17 UVLO Protection

TPS51125 has VREG5 undervoltage lockout protection (UVLO). When the VREG5 voltage is lower than UVLO threshold voltage both switch mode power supplies are shut off. This is nonlatch protection. When the VREG3 voltage is lower than (VO2 - 1 V), both switch mode power supplies are also shut off.

7.3.18 Thermal Shutdown

TPS51125 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 150°C), TPS51125 is shut off including LDOs. This is nonlatch protection.

7.4.1 Enable and Soft-Start

EN0 is the control pin of VREG5, VREG3 and VREF regulators. Bring this node down to GND disables those three regulators and minimize the shutdown supply current to 10 μA. Pulling this node up to 3.3 V or 5 V will turn the three regulators on to standby mode. The two switch mode power supplies (channel-1, channel-2) become ready to enable at this standby mode. The TPS51125 has an internal, 1.6 ms, voltage servo softstart for each channel. When the ENTRIPx pin becomes higher than the enable threshold voltage, which is typically 430 mV, an internal DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the output voltage is maintained during start up. As TPS51125 shares one DAC with both channels, if ENTRIPx pin becomes higher than the enable threshold voltage while another channel is starting up, soft start is postponed until another channel soft start has completed. If both of ENTRIP1 and ENTRIP2 become higher than the enable threshold voltage at a same time (within 60 μs), both channels start up at same time.