SLUS786H OCTOBER   2007  – January 2015 TPS51125

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PWM Operations
      2. 7.3.2  Adaptive On-Time Control and PWM Frequency
      3. 7.3.3  Loop Compensation
      4. 7.3.4  Ramp Signal
      5. 7.3.5  Light-Load Condition in Auto-Skip Operation
      6. 7.3.6  Out-of-Audio Light-Load Operation
      7. 7.3.7  VREG5/VREG3 Linear Regulators
      8. 7.3.8  VREG5 Switch Over
      9. 7.3.9  VREG3 Switch Over
      10. 7.3.10 Powergood
      11. 7.3.11 Output Discharge Control
      12. 7.3.12 Low-Side Driver
      13. 7.3.13 High-Side Driver
      14. 7.3.14 VCLK for Charge Pump
      15. 7.3.15 Current Protection
      16. 7.3.16 Overvoltage and Undervoltage Protection
      17. 7.3.17 UVLO Protection
      18. 7.3.18 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable and Soft-Start
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Determine Output Voltage
        2. 8.2.2.2 Choose the Inductor
        3. 8.2.2.3 Choose the Output Capacitors
        4. 8.2.2.4 Choose the Low-Side MOSFET
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Input voltage(1) VBST1, VBST2 –0.3 36 V
VIN –0.3 30
LL1, LL2 –2.0 30
LL1, LL2, pulse width < 20 ns –5.0 30
VBST1, VBST2 (2) –0.3 6
EN0, ENTRIP1, ENTRIP2, VFB1, VFB2, VO1, VO2, TONSEL, SKIPSEL –0.3 6
Output voltage(1) DRVH1, DRVH2 –1.0 36
DRVH1, DRVH2(2) –0.3 6
PGOOD, VCLK, VREG3, VREG5, VREF, DRVL1, DRVL2 –0.3 6
Junction temperature, TJ –40 125 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltage values are with respect to the corresponding LLx terminal.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage VIN 5.5 28 V
Input voltage VBST1, VBST2 –0.1 34
VBST1, VBST2 (with respect to LLx) –0.1 5.5
EN0, ENTRIP1, ENTRIP2, VFB1, VFB2, VO1, VO2, TONSEL, SKIPSEL –0.1 5.5
Output voltage DRVH1, DRVH2 –0.8 34
DRVH1, DRVH2 (with respect to LLx) –0.1 5.5
LL1, LL2 –1.8 28
VREF, VREG3, VREG5 –0.1 5.5
PGOOD, VCLK, DRVL1, DRVL2 –0.1 5.5
Operating free-air temperature –40 85 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS51125 UNIT
VQFN
24 PINS
RθJA Junction-to-ambient thermal resistance 34.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 37.2
RθJB Junction-to-board thermal resistance 12.4
ψJT Junction-to-top characterization parameter 0.4
ψJB Junction-to-board characterization parameter 12.4
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IVIN1 VIN supply current1 VIN current, TA = 25°C, no load, VO1 = 0 V, VO2 = 0 V, EN0=open, ENTRIPx = 5 V,
VFB1 = VFB2 = 2.05 V		 0.55 1 mA
IVIN2 VIN supply current2 VIN current, TA = 25°C, no load, VO1 = 5 V, VO2 = 3.3 V, EN0=open, ENTRIPx = 5 V,
VFB1 = VFB2 = 2.05 V		 4 6.5 μA
IVO1 VO1 current VO1 current, TA = 25°C, no load, VO1 = 5 V, VO2 = 3.3 V, EN0=open, ENTRIPx = 5 V,
VFB1 = VFB2 = 2.05 V		 0.8 1.5 mA
IVO2 VO2 current VO2 current, TA = 25°C, no load, VO1 = 5 V, VO2 = 3.3 V, EN0=open, ENTRIPx = 5 V,
VFB1 = VFB2 = 2.05 V		 12 100 μA
IVINSTBY VIN standby current VIN current, TA = 25°C, no load,
EN0 = 1.2 V, ENTRIPx = 0 V		 95 250
IVINSDN VIN shutdown current VIN current, TA = 25°C, no load,
EN0 = ENTRIPx = 0 V		 10 25
VREF OUTPUT
VVREF VREF output voltage IVREF = 0 A 1.98 2.00 2.02 V
-5 μA < IVREF < 100 μA 1.97 2.00 2.03
VREG5 OUTPUT
VVREG5 VREG5 output voltage VO1 = 0 V, IVREG5 < 100 mA, TA = 25°C 4.8 5 5.2 V
VO1 = 0 V, IVREG5 < 100 mA, 6.5 V < VIN < 28 V 4.75 5 5.25
VO1 = 0 V, IVREG5 < 50 mA, 5.5 V < VIN < 28 V 4. 75 5 5.25
IVREG5 VREG5 output current VO1 = 0 V, VREG5 = 4.5 V 100 175 250 mA
VTH5VSW Switch over threshold Turns on 4.55 4.7 4.85 V
Hysteresis 0.15 0.25 0.3
R5VSW 5 V SW RON VO1 = 5 V, IVREG5 = 100 mA 1 3 Ω
VREG3 OUTPUT
VVREG3 VREG3 output voltage VO2 = 0 V, IVREG3 < 100 mA, TA= 25°C 3.2 3.33 3.46 V
VO2 = 0 V, IVREG3 < 100 mA, 6.5 V < VIN < 28 V 3.13 3.33 3.5
VO2 = 0 V, IVREG3 < 50 mA, 5.5 V < VIN < 28 V 3.13 3.33 3.5
IVREG3 VREG3 output current VO2 = 0 V, VREG3 = 3 V 100 175 250 mA
VTH3VSW Switch over threshold Turns on 3.05 3.15 3.25 V
Hysteresis 0.1 0.2 0.25
R3VSW 3 V SW RON VO2 = 3.3 V, IVREG3 = 100 mA 1.5 4 Ω
INTERNAL REFERENCE VOLTAGE
VIREF Internal reference voltage IVREF = 0 A, beginning of ON state 1.95 1.98 2.01 V
VVFB VFB regulation voltage FB voltage, IVREF = 0 A, skip mode 1.98 2.01 2.04
FB voltage, IVREF = 0 A, OOA mode (1) 2.00 2.035 2.07
FB voltage, IVREF = 0 A, continuous conduction (1) 2.00
IVFB VFB input current VFBx = 2.0 V, TA= 25°C –20 20 nA
VOUT DISCHARGE
IDischg VOUT discharge current ENTRIPx = 0 V, VOx = 0.5 V 10 60 mA
OUTPUT DRIVERS
RDRVH DRVH resistance Source, VBSTx - DRVHx = 100 mV 4 8 Ω
Sink, VDRVHx - LLx = 100 mV 1.5 4
RDRVL DRVL resistance Source, VVREG5 - DRVLx = 100 mV 4 8
Sink, VDRVLx = 100 mV 1.5 4
tD Dead time DRVHx-off to DRVLx-on 10 ns
DRVLx-off to DRVHx-on 30
CLOCK OUTPUT
VCLKH High level voltage IVCLK = -10 mA, VO1 = 5 V, TA = 25 °C 4.84 4.92 V
VCLKL Low level voltage IVCLK = 10 mA, VO1 = 5 V, TA = 25 °C 0.06 0.12
fCLK Clock frequency TA = 25 °C 175 270 325 kHz
INTERNAL BST DIODE
VFBST Forward voltage VVREG5-VBSTx, IF = 10 mA, TA = 25 °C 0.7 0.8 0.9 V
IVBSTLK VBST leakage current VBSTx = 34 V, LLx = 28 V, TA = 25 °C 0.1 1 μA
DUTY AND FREQUENCY CONTROL
tON11 CH1 on time 1 VIN = 12 V, VO1 = 5 V, 200 kHz setting 2080 ns
tON12 CH1 on time 2 VIN = 12 V, VO1 = 5 V, 245 kHz setting 1700
tON13 CH1 on time 3 VIN = 12 V, VO1 = 5 V, 300 kHz setting 1390
tON14 CH1 on time 4 VIN = 12 V, VO1 = 5 V, 365 kHz setting 1140
tON21 CH2 on time 1 VIN = 12 V, VO2 = 3.3 V, 250 kHz setting 1100
tON22 CH2 on time 2 VIN = 12 V, VO2 = 3.3 V, 305 kHz setting 900
tON23 CH2 on time 3 VIN = 12 V, VO2 = 3.3 V, 375 kHz setting 730
tON24 CH2 on time 4 VIN = 12 V, VO2 = 3.3 V, 460 kHz setting 600
tON(min) Minimum on time TA = 25 °C 80
tOFF(min) Minimum off time TA = 25 °C 300
SOFT-START
tSS Internal SS time Internal soft start 1.1 1.6 2.1 ms
POWERGOOD
VTHPG PG threshold PG in from lower 92.50% 95% 97.50%
PG in from higher 102.50% 105% 107.50%
PG hysteresis 2.50% 5% 7.50%
IPGMAX PG sink current PGOOD = 0.5 V 5 12 mA
tPGDEL PG delay Delay for PG in 350 510 670 μs
LOGIC THRESHOLD AND SETTING CONDITIONS
VEN0 EN0 setting voltage Shutdown 0.4 V
Enable, VCLK = off 0.8 1.6
Enable, VCLK = on 2.4
IEN0 EN0 current VEN0 = 0.2 V 2 3.5 5 μA
VEN0 = 1.5 V 1 1.75 2.5
VEN ENTRIP1, ENTRIP2 threshold Shutdown 350 400 450 mV
Hysteresis 10 30 60
VTONSEL TONSEL setting voltage 200 kHz/250 kHz 1.5 V
245 kHz/305 kHz 1.9 2.1
300 kHz/375 kHz 2.7 3.6
365 kHz/460 kHz 4.7
VSKIPSEL SKIPSEL setting voltage PWM only 1.5
Auto skip 1.9 2.1
OOA auto skip 2.7
PROTECTION: CURRENT SENSE
IENTRIP ENTRIPx source current VENTRIPx = 920 mV, TA= 25°C 9.4 10 10.6 μA
TCIENTRIP ENTRIPx current temperature coefficient On the basis of 25°C(1) 4500 ppm/°C
VOCLoff OCP comparator offset ((VENTRIPx-GND/9)-24 mV -VGND-LLx) voltage, VENTRIPx-GND = 920 mV –8 0 8 mV
VOCL(max) Maximum OCL setting VENTRIPx = 5 V 185 205 225
VZC Zero cross detection comparator offset VGND-LLx voltage –5 0 5
VENTRIP Current limit threshold VENTRIPx-GND voltage, (1) 0.515 2 V
PROTECTION: UNDERVOLTAGE AND OVERVOLTAGE
VOVP OVP trip threshold OVP detect 110% 115% 120%
tOVPDEL OVP prop delay 2 μs
VUVP Output UVP trip threshold UVP detect 55% 60% 65%
Hysteresis 10%
tUVPDEL Output UVP prop delay 20 32 40 μs
tUVPEN Output UVP enable delay 1.4 2 2.6 ms
UVLO
VUVVREG5 VREG5 UVLO threshold Wake up 4.1 4.2 4.3 V
Hysteresis 0.38 0.43 0.48
VUVVREG3 VREG3 UVLO threshold Shutdown (1) VO2-1
THERMAL SHUTDOWN
TSDN Thermal shutdown threshold Shutdown temperature (1) 150 °C
Hysteresis (1) 10
(1) Ensured by design. Not production tested.

6.6 Typical Characteristics

fig1_lus786.gif
Figure 1. VIN Supply Current1 vs Junction Temperature
fig3_lus786.gif
Figure 3. VIN Supply Current2 vs Junction Temperature
fig5_lus786.gif
Figure 5. VIN Standby Current vs Junction Temperature
fig7_lus786.gif
Figure 7. VIN Shutdown Current vs Junction Temperature
fig9_lus786.gif
Figure 9. Current Sense Current vs Junction Temperature
fig11_lus786.gif
Figure 11. Switching Frequency vs Input Voltage
fig13_lus786.gif
Figure 13. Switching Frequency vs Input Voltage
fig15_lus786.gif
Figure 15. Switching Frequency vs Output Current
fig17_lus786.gif
Figure 17. Switching Frequency vs Output Current
fig19_lus786.gif
Figure 19. OVP/UVP Threshold Voltage vs Junction Temperature
fig21_lus786.gif
Figure 21. VREG5 Output Voltage vs Output Current
fig23_lus786.gif
Figure 23. 5-V Output Voltage vs Output Current
fig25_lus786.gif
Figure 25. 5-V Output Voltage vs Input Voltage
fig27_lus786.gif
Figure 27. 5-V Efficiency vs Output Current
fig2new2_lus786.gif
Figure 2. VIN Supply Current1 vs Input Voltage
fig4_lus786.gif
Figure 4. VIN Supply Current1 vs Input Voltage
fig6_lus786.gif
Figure 6. VIN Standby Current vs Input Voltage
fig8_lus786.gif
Figure 8. VIN Shutdown Current vs Input Voltage
fig10_lus786.gif
Figure 10. VCLK Frequency vs Junction Temperature
fig12_lus786.gif
Figure 12. Switching Frequency vs Input Voltage
fig14_lus786.gif
Figure 14. Switching Frequency vs Input Voltage
fig16_lus786.gif
Figure 16. Switching Frequency vs Output Current
fig18_lus786.gif
Figure 18. Switching Frequency vs Output Current
fig20_lus786.gif
Figure 20. VREG5 Output Voltage vs Output Current
fig22_lus786.gif
Figure 22. VREG5 Output Voltage vs Output Current
fig24_lus786.gif
Figure 24. 3.3-V Output Voltage vs Output Current
fig26_lus786.gif
Figure 26. 3.3-V Output Voltage vs Input Voltage
fig28_lus786.gif
Figure 28. 3.3-V Efficiency vs Output Current