SLUS812D February   2008  – February 2020 TPS51200

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified DDR Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Sink and Source Regulator (VO Pin)
      2. 7.3.2  Reference Input (REFIN Pin)
      3. 7.3.3  Reference Output (REFOUT Pin)
      4. 7.3.4  Soft-Start Sequencing
      5. 7.3.5  Enable Control (EN Pin)
      6. 7.3.6  Powergood Function (PGOOD Pin)
      7. 7.3.7  Current Protection (VO Pin)
      8. 7.3.8  UVLO Protection (VIN Pin)
      9. 7.3.9  Thermal Shutdown
      10. 7.3.10 Tracking Start-up and Shutdown
      11. 7.3.11 Output Tolerance Consideration for VTT DIMM Applications
      12. 7.3.12 REFOUT (VREF) Consideration for DDR2 Applications
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Input Voltage Applications
      2. 7.4.2 S3 and Pseudo-S5 Support
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Voltage Capacitor
        2. 8.2.2.2 VLDO Input Capacitor
        3. 8.2.2.3 Output Capacitor
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 3.3-VIN, DDR2 Configuration
      2. 8.3.2 2.5-VIN, DDR3 Configuration
      3. 8.3.3 3.3-VIN, LP DDR3 or DDR4 Configuration
      4. 8.3.4 3.3-VIN, DDR3 Tracking Configuration
      5. 8.3.5 3.3-VIN, LDO Configuration
      6. 8.3.6 3.3-VIN, DDR3 Configuration with LFP
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Design Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Evaluation Modules
        2. 11.1.2.2 Spice Models
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Over recommended free-air temperature range, VVIN = 3.3 V, VVLDOIN = 1.8 V, VREFIN = 0.9 V, VVOSNS = 0.9 V, VEN = VVIN, COUT = 3 × 10 μF and circuit shown in Figure 24. (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IIN Supply current TA = 25 °C, VEN = 3.3 V, No Load 0.7 1 mA
IIN(SDN) Shutdown current TA = 25 °C, VEN = 0 V, VREFIN = 0,
No Load		 65 80 μA
TA = 25 °C, VEN = 0 V, VREFIN > 0.4 V, No Load 200 400
ILDOIN Supply current of VLDOIN TA = 25 °C, VEN = 3.3 V, No Load 1 50 μA
ILDOIN(SDN) Shutdown current of VLDOIN TA = 25 °C, VEN = 0 V, No Load 0.1 50 μA
INPUT CURRENT
IREFIN Input current, REFIN VEN = 3.3 V 1 μA
VO OUTPUT
VVOSNS Output DC voltage, VO VREFOUT = 1.25 V (DDR1), IO = 0 A 1.25 V
–15 15 mV
VREFOUT = 0.9 V (DDR2), IO = 0 A 0.9 V
–15 15 mV
VREFOUT = 0.75 V (DDR3), IO = 0 A 0.75 V
–15 15 mV
VREFOUT = 0.675 V (DDR3L), IO = 0 A 0.675 V
–15 15 mV
VREFOUT = 0.6 V (DDR4), IO = 0 A 0.6 V
–15 15 mV
VVOTOL Output voltage tolerance to REFOUT –2 A < IVO < 2 A –25 25 mV
IVOSRCL VO source current Limit With reference to REFOUT,
VOSNS = 90% × VREFOUT 		3 4.5 A
IVOSNCL VO sink current Limit With reference to REFOUT,
VOSNS = 110% × VREFOUT 		3.5 5.5 A
IDSCHRG Discharge current, VO VREFIN = 0 V, VVO = 0.3 V, VEN = 0 V, TA = 25°C 18 25 Ω
POWERGOOD COMPARATOR
VTH(PG) VO PGOOD threshold PGOOD window lower threshold with respect to REFOUT –23.5% –20% –17.5%
PGOOD window upper threshold with respect to REFOUT 17.5% 20% 23.5%
PGOOD hysteresis 5%
tPGSTUPDLY PGOOD start-up delay Start-up rising edge, VOSNS within 15% of REFOUT 2 ms
VPGOODLOW Output low voltage ISINK = 4 mA 0.4 V
tPBADDLY PGOOD bad delay VOSNS is outside of the ±20% PGOOD window 10 μs
IPGOODLK Leakage current(1) VOSNS = VREFIN (PGOOD high impedance), VPGOOD = VVIN + 0.2 V 1 μA
REFIN AND REFOUT
VREFIN REFIN voltage range 0.5 1.8 V
VREFINUVLO REFIN undervoltage lockout REFIN rising 360 390 420 mV
VREFINUVHYS REFIN undervoltage lockout hysteresis 20 mV
VREFOUT REFOUT voltage REFIN V
VREFOUTTOL REFOUT voltage tolerance to VREFIN –1 mA < IREFOUT < 1 mA,
VREFIN = 1.25 V		 –12 12 mV
–1 mA < IREFOUT < 1 mA,
VREFIN = 0.9 V		 –12 12
–1 mA < IREFOUT < 1 mA,
VREFIN = 0.75 V		 –12 12
–1 mA < IREFOUT < 1 mA,
VREFIN = 0.675 V		 –12 12
–1 mA < IREFOUT < 1 mA,
VREFIN = 0.6 V		 –12 12
IREFOUTSRCL REFOUT source current limit VREFOUT = 0 V 10 40 mA
IREFOUTSNCL REFOUT sink current limit VREFOUT = 0 V 10 40 mA
UVLO AND EN LOGIC THRESHOLD
VVINUVVIN UVLO threshold Wake up, TA = 25°C 2.2 2.3 2.375 V
Hysteresis 50 mV
VENIH High-level input voltage Enable 1.7 V
VENIL Low-level input voltage Enable 0.3
VENYST Hysteresis voltage Enable 0.5
IENLEAK Logic input leakage current EN, TA = 25°C –1 1 μA
THERMAL SHUTDOWN
TSON Thermal shutdown threshold(1) Shutdown temperature 150 °C
Hysteresis 25
(1) Ensured by design. Not production tested.