SLUS812D February   2008  – February 2020 TPS51200

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified DDR Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Sink and Source Regulator (VO Pin)
      2. 7.3.2  Reference Input (REFIN Pin)
      3. 7.3.3  Reference Output (REFOUT Pin)
      4. 7.3.4  Soft-Start Sequencing
      5. 7.3.5  Enable Control (EN Pin)
      6. 7.3.6  Powergood Function (PGOOD Pin)
      7. 7.3.7  Current Protection (VO Pin)
      8. 7.3.8  UVLO Protection (VIN Pin)
      9. 7.3.9  Thermal Shutdown
      10. 7.3.10 Tracking Start-up and Shutdown
      11. 7.3.11 Output Tolerance Consideration for VTT DIMM Applications
      12. 7.3.12 REFOUT (VREF) Consideration for DDR2 Applications
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Input Voltage Applications
      2. 7.4.2 S3 and Pseudo-S5 Support
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Voltage Capacitor
        2. 8.2.2.2 VLDO Input Capacitor
        3. 8.2.2.3 Output Capacitor
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 3.3-VIN, DDR2 Configuration
      2. 8.3.2 2.5-VIN, DDR3 Configuration
      3. 8.3.3 3.3-VIN, LP DDR3 or DDR4 Configuration
      4. 8.3.4 3.3-VIN, DDR3 Tracking Configuration
      5. 8.3.5 3.3-VIN, LDO Configuration
      6. 8.3.6 3.3-VIN, DDR3 Configuration with LFP
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Design Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Evaluation Modules
        2. 11.1.2.2 Spice Models
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.3 Thermal Design Considerations

Because the TPS51200 is a linear regulator, the VO current flows in both source and sink directions, thereby dissipating power from the device. When the device is sourcing current, the voltage difference shown in Equation 5 calculates the power dissipation.

Equation 5. TPS51200 q_pdsrc_slus812.gif

In this case, if the VLDOIN pin is connected to an alternative power supply lower than the VDDQ voltage, overall power loss can be reduced. During the sink phase, the device applies the VO voltage across the internal LDO regulator. Equation 6 calculates he power dissipation, PD_SNK can be calculated by .

Equation 6. TPS51200 q_pdsnk_slus812.gif

Because the device does not sink and source current at the same time and the I/O current may vary rapidly with time, the actual power dissipation should be the time average of the above dissipations over the thermal relaxation duration of the system. The current used for the internal current control circuitry from the VIN supply and the VLDOIN supply are other sources of power consumption. This power can be estimated as 5 mW or less during normal operating conditions and must be effectively dissipated from the package.

Maximum power dissipation allowed by the package is calculated by Equation 7.

Equation 7. TPS51200 q_ppkg_slus812.gif

where

  • TJ(max) is 125°C
  • TA(max) is the maximum ambient temperature in the system
  • θJA is the thermal resistance from junction to ambient

NOTE

Because Equation 7 demonstrates the effects of heat spreading in the ground plane, use it as a guideline only. Do not use Equation 7 to estimate actual thermal performance in real application environments.

In an application where the device is mounted on PCB, TI strongly recommends using ψJT and ψJB, as explained in the section pertaining to estimating junction temperature in the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Using the thermal metrics ψJT and ψJB, as shown in the Thermal Information table, estimate the junction temperature with corresponding formulas shown in Equation 8. The older θJC top parameter specification is listed as well for the convenience of backward compatibility.

Equation 8. TPS51200 q_tj1_slus812.gif
Equation 9. TPS51200 q_tj2_slus812.gif

where

  • PD is the power dissipation shown in Equation 5 and Equation 6
  • TT is the temperature at the center-top of the IC package
  • TB is the PCB temperature measured 1-mm away from the thermal pad package on the PCB surface (see Figure 36).

NOTE

Both TT and TB can be measured on actual application boards using a thermo-gun (an infrared thermometer). For more information about measuring TT and TB, see the application report Using New Thermal Metrics (SBVA025).

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TPS51200 v08018_lus812.gifFigure 35. Recommended Land Pad Pattern
TPS51200 package_measure_slus812.gifFigure 36. Package Thermal Measurement