8.2.1.2.4 Output Tolerance Consideration for VTT DIMM Applications

Figure 22 shows the typical characteristics for a single memory cell.

Figure 22. DDR Physical Signal System Bi-Directional SSTL Signaling

In Figure 22, when Q1 is on and Q2 is off:

• The current flows from VDDQ via the termination resistor to VTT
• VTT sinks current

• The current flows from VTT via the termination resistor to GND
• VTT sources current

Because VTT accuracy has a direct impact on the memory signal integrity, it is imperative to understand the tolerance requirement on VTT. Based on JEDEC VTT specifications for DDR and DDR2 (JEDEC standard: DDR JESD8-9B May 2002; DDR2 JESD8-15A Sept 2003).

VTTREF – 40 mV < VTT < VTTREF + 40 mV, for both DC and AC conditions

The specification indicates that VTT must keep track of VTTREF for proper signal conditioning.

The TPS51200A-Q1 device ensures the regulator output voltage to be:

VTTREF –25 mV < VTT < VTTREF + 25 mV, for both DC and AC conditions and –2 A < I_VTT < 2 A

The regulator output voltage is measured at the regulator side, not the load side. The tolerance is applicable to DDR, DDR2, DDR3 and low-power DDR3/DDR4 applications (see Table 1 for detailed information). To meet the stability requirement, a minimum output capacitance of 20 μF is needed. Considering the actual tolerance on the MLCC capacitors, three 10-μF ceramic capacitors are sufficient to meet the above requirement.

The TPS51200A-Q1 device is designed as a Gm driven LDO. The voltage droop between the reference input and the output regulator is determined by the transconductance and output current of the device. The typical Gm is 250 S at 2 A and changes with respect to the load to conserve the quiescent current (that is, the Gm is very low at no load condition). The Gm LDO regulator is a single pole system. Its unity gain bandwidth for the voltage loop is only determined by the output capacitance, as a result of the bandwidth nature of the Gm (see Equation 1).

Equation 1.

where

• F_UGBW is the unity gain bandwidth
• Gm is transconductance
• C_OUT is the output capacitance

This type of regulator has two limitations on the output bulk capacitor requirement. To maintain stability, the zero location contributed by the ESR of the output capacitors must be greater than the –3-dB point of the current loop. This constraint means that higher ESR capacitors must not be used in the design. In addition, the impedance characteristics of the ceramic capacitor must be well understood to prevent the gain peaking effect around the Gm –3-dB point because of the large ESL, the output capacitor and parasitic inductance of the VO trace.

Figure 23. Bode Plot for a Typical DDR3 Configuration

Figure 23 shows the bode plot simulation for a typical DDR3 configuration of the TPS51200A-Q1 device, where:

• V_IN = 3.3 V
• V_VLDOIN = 1.5 V
• V_VO = 0.75 V
• I_IO = 2 A
• 3 × 10-μF capacitors included
• ESR = 2.5 mΩ
• ESL = 800 pH

The unity-gain bandwidth is approximately 1 MHz and the phase margin is 52°. The 0-dB level is crossed, the gain peaks because of the ESL effect. However, the peaking is kept well below 0 dB.

Figure 24 shows the load regulation and Figure 25 shows the transient response for a typical DDR3 configuration. When the regulator is subjected to ±1.5-A load step and release, the output voltage measurement shows no difference between the DC and AC conditions.