SLUSDW9A June   2020  – June 2020 TPS51215A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Switch Mode Power Supply Control
      2. 7.3.2  VREF, V0, V1, V2, V3 and Output Voltage
      3. 7.3.3  Soft-Start and Power Good
      4. 7.3.4  SLEW and VID Function
      5. 7.3.5  MODE Pin Configuration
      6. 7.3.6  Light-Load Operation
      7. 7.3.7  Out-of-Bound Operation
      8. 7.3.8  Current Sensing and Overcurrent Protection
      9. 7.3.9  Overvoltage and Undervoltage Protection
      10. 7.3.10 V5IN Undervoltage Lockout Protection
      11. 7.3.11 Thermal Shutdown
    4. 7.4 D-CAP2 Control Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
  9. 9 Typical Applications
    1. 9.1 Design Requirements
    2. 9.2 Detailed Design Procedure
      1. 9.2.1 Step One: Determine the Specifications
      2. 9.2.2 Step Two: Determine System Parameters
      3. 9.2.3 Step Three: Determine Inductor Value and Choose Inductor
      4. 9.2.4 Step Four: Set the Output Voltages
      5. 9.2.5 Step Five: Calculate SLEW Capacitance
      6. 9.2.6 Step Six
      7. 9.2.7 Step Seven: Determine the Output Capacitance
      8. 9.2.8 Step Eight: Select Decoupling and Peripheral Components
    3. 9.3 Application Examples
      1. 9.3.1 Design 1: 2-Bit VID ICC(max) = 30 A, DCAP2 600-kHz Application for VCCIN_AUX in Intel TigerLake platform
      2. 9.3.2 Design 2: 2-Bit VID, ICC(max) = 10 A, for VCCIO_1_2 in Intel RocketLake - S platform
    4. 9.4 Application Curves of Design 1
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information
      2. 13.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3 Soft-Start and Power Good

Prior to asserting EN high, the power stage conversion voltage and V5IN voltage should be ready. When EN is asserted high, TPS51215A provides soft start to suppress in-rush current during start-up. The soft start action is achieved by an internal SLEW current of 4.5 µA (typ) sourcing into a external MLCC capacitor connected from SLEW pin to GND.

Use Equation 1 to determine the soft-start timing.

Equation 1. TPS51215A q_dt_lusao8.gif

where

  • CSLEW is the soft start capacitance
  • VOUT is the output voltage
  • ISLEW is the internal 4.5-µA current source

The TPS51215A has a open-drain PowerGood output pin that indicates the Vout voltage is within the target range. The target voltage window and transition delay times of the PGOOD comparator are ±8% (typ) and 1-ms delay for assertion from low to high, and ±16% (typ) and 0.2-µs delay for de-assertion from high to low during operation.