SLUSFR0A July   2024  – August 2024 TPS51375

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  PWM Operation and D-CAP3™ Control Mode
      2. 6.3.2  Remote Sense
      3. 6.3.3  Body Braking
      4. 6.3.4  5V LDO and BYP Function
      5. 6.3.5  Soft Start
      6. 6.3.6  Large Duty Operation
      7. 6.3.7  Power Good
      8. 6.3.8  Overcurrent Protection and Undervoltage Protection
      9. 6.3.9  Overvoltage Protection
      10. 6.3.10 UVLO Protection
      11. 6.3.11 Output Voltage Discharge
      12. 6.3.12 Standby Operation
      13. 6.3.13 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Advanced Eco-mode Control
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Custom Design With WEBENCH® Tools
        2. 7.2.2.2 External Component Selection
          1. 7.2.2.2.1 Remote Sense Amplifier and Adjusting the Output Voltage
          2. 7.2.2.2.2 Inductor Selection
          3. 7.2.2.2.3 Output Capacitor Selection
          4. 7.2.2.2.4 Input Capacitor Selection
          5. 7.2.2.2.5 Bootstrap Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

  • Make note that the PCB layout of any DC/DC converter is critical to the excellent performance of the design. Bad PCB layout can disrupt the operation of a good schematic design. Even if the converter regulates correctly, bad PCB layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore, the EMI performance of the converter is dependent on the PCB layout to a great extent. In a buck converter, the most critical PCB feature is the loop formed by the input capacitors and power ground. This loop carries large transient currents that can cause large transient voltages when reacting with the trace inductance. These unwanted transient voltages disrupt the proper operation of the converter. Because of this fact, the traces in this loop must be wide and short, and the loop area as small as possible to reduce the parasitic inductance.
  • Use a four-layer PCB for good thermal performance and with maximum ground plane. 3-inch × 2.75-inch, top and bottom layer PCB with 2oz copper is used as example.
  • Place the decoupling capacitors right across VIN and VCC as close as possible.
  • Place output inductors and capacitors with IC at the same layer. The SW routing must be as short as possible to minimize EMI, and must be a width plane to carry big current. Enough vias must be added to the PGND connection of output capacitors and also as close to the output pin as possible.
  • Place BST resistor and capacitor with IC at the same layer, close to BST and SW plane. TI recommends > 10-mil width trace to reduce line parasitic inductance.
  • Make feedback 10 mil and routed away from the switching node, BST node, or other high speed digital signal.
  • Make VIN trace wide to reduce the trace impedance and provide enough current capability.
  • Place multiple vias under the device near VIN and PGND and near input capacitors to reduce parasitic inductance and improve thermal performance.