SLUSDX7A September   2020  – October 2020 TPS51397A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Operation and DCAP3 Control
      2. 7.3.2 Soft Start
      3. 7.3.3 Large Duty Operation
      4. 7.3.4 Power Good
      5. 7.3.5 Overcurrent Protection and Undervoltage Protection
      6. 7.3.6 Overvoltage Protection
      7. 7.3.7 UVLO Protection
      8. 7.3.8 Output Voltage Discharge
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Light Load Operation
      2. 7.4.2 Advanced Eco-mode Control
      3. 7.4.3 Out-of-Audio
      4. 7.4.4 Mode Selection
      5. 7.4.5 Standby Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Component Selection
          1. 8.2.2.1.1 Output Voltage Set Point
          2. 8.2.2.1.2 MODE Selection
          3. 8.2.2.1.3 Inductor Selection
          4. 8.2.2.1.4 Output Capacitor Selection
          5. 8.2.2.1.5 Input Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1 Layout Guidelines

  • A four-layer PCB is recommended for good thermal performance and with maximum ground plane. 3-inch × 2.75-inch, top and bottom layer PCB with 2-oz copper is used as example.
  • Place the decoupling capacitors right across VIN and VCC as close as possible.
  • Place output inductors and capacitors with IC at the same layer. SW routing should be as short as possible to minimize EMI, and should be a width plane to carry big current, enough vias should be added to the PGND connection of output capacitors and also as close to the output pin as possible.
  • Place BST resistor and capacitor with IC at the same layer, close to BST and SW plane. >10-mil width trace is recommended to reduce line parasitic inductance.
  • Feedback can be 10 mil and must be routed away from the switching node, BST node, or other high speed digital signal.
  • VIN trace must be wide to reduce the trace impedance and provide enough current capability.
  • Place multiple vias under the device near VIN and PGND and near input capacitors to reduce parasitic inductance and improve thermal performance.