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  • TPS51716 Complete DDR2, DDR3, DDR3L, LPDDR3, and DDR4 Memory Power Solution Synchronous Buck Controller, 2-A LDO, With Buffered Reference

    • SLUSB94A OCTOBER   2012  – September 2016 TPS51716

      PRODUCTION DATA.  

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  • TPS51716 Complete DDR2, DDR3, DDR3L, LPDDR3, and DDR4 Memory Power Solution Synchronous Buck Controller, 2-A LDO, With Buffered Reference
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VDDQ Switch Mode Power Supply Control
      2. 7.3.2  VREF and REFIN, VDDQ Output Voltage
      3. 7.3.3  Soft-Start and Powergood
      4. 7.3.4  Power State Control
      5. 7.3.5  VDDQ Overvoltage and Undervoltage Protection
      6. 7.3.6  VDDQ Out-of-Bound Operation
      7. 7.3.7  VDDQ Overcurrent Protection
      8. 7.3.8  VTT and VTTREF
      9. 7.3.9  VTT Overcurrent Protection
      10. 7.3.10 V5IN Undervoltage Lockout (UVLO) Protection
      11. 7.3.11 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE Pin Configuration
      2. 7.4.2 Discharge Control
      3. 7.4.3 D-CAP2 Mode Operation
      4. 7.4.4 Light-Load Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Components Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Receiving Notification of Documentation Updates
      2. 11.2.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • RUK|20
    • MPQF220D
Thermal pad, mechanical data (Package|Pins)
  • RUK|20
    • QFND191D
Orderable Information
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  • slusb94a_pm
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DATA SHEET

TPS51716 Complete DDR2, DDR3, DDR3L, LPDDR3, and DDR4 Memory Power Solution Synchronous Buck Controller, 2-A LDO, With Buffered Reference

1 Features

  • Synchronous Buck Controller (VDDQ)
    • Conversion Voltage Range: 3 to 28 V
    • Output Voltage Range: 0.7 to 1.8 V
    • 0.8% VREF Accuracy
    • D-CAP2™ Mode for Ceramic Output Capacitors
    • Selectable 500-kHz/670-kHz Switching Frequencies
    • Optimized Efficiency at Light and Heavy Loads With Auto-Skip Function
    • Supports Soft-Off in S4/S5 States
    • OCL/OVP/UVP/UVLO Protections
    • Powergood Output
  • 2-A LDO (VTT), Buffered Reference (VTTREF)
    • 2-A (Peak) Sink and Source Current
    • Requires Only 10-μF of Ceramic Output Capacitance
    • Buffered, Low Noise, 10-mA VTTREF Output
    • 0.8% VTTREF, 20-mV VTT Accuracy
    • Support High-Z in S3 and Soft-Off in S4/S5
  • Thermal Shutdown
  • 20-Pin, 3 mm × 3 mm, WQFN Package

2 Applications

  • DDR2, DDR3, DDR3L, LPDDR3, and DDR4 Memory Power Supplies
  • SSTL_18, SSTL_15, SSTL_135, and HSTL Termination

3 Description

The TPS51716 provides a complete power supply for DDR2, DDR3, DDR3L, LPDDR3, and DDR4 memory systems in the lowest total cost and minimum space. It integrates a synchronous buck regulator controller (VDDQ) with a 2-A sink/source tracking LDO (VTT) and buffered low noise reference (VTTREF). The TPS51716 employs D-CAP2 mode coupled with 500 kHz or 670 kHz operating frequencies that supports ceramic output capacitors without an external compensation circuit. The VTTREF tracks VDDQ/2 with excellent 0.8% accuracy. The VTT, which provides 2-A sink/source peak current capabilities, requires only 10 μF of ceramic capacitance. In addition, the device features a dedicated LDO supply input.

The TPS51716 provides rich, useful functions as well as excellent power supply performance. It supports flexible power state control, placing VTT at high-Z in S3 and discharging VDDQ, VTT and VTTREF (soft-off) in S4/S5 state. It includes programmable OCL with low-side MOSFET RDS(on) sensing, OVP/UVP/UVLO and thermal shutdown protections.

TI offers the TPS51716 in a 20-pin, 3 mm × 3 mm, WQFN package and specifies it for an ambient temperature range between –40°C and 85°C.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPS51716 WQFN (20) 3.00 mm × 3.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Block Diagram

TPS51716 v12146_lusb94.gif

4 Revision History

Changes from * Revision (October 2012) to A Revision

  • Added ESD Ratings table, Detailed Description section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
  • Updated the Title From: Complete DDR2, DDR3, DDR3L, and LPDDR3 Memory Power Solution To: Complete DDR2, DDR3, DDR3L, LPDDR3, and DDR4 Memory Power Go
  • Changed Applications list From: DDR2/DDR3/DDR3L/LPDDR3 Memory Power Supplies To: DDR2, DDR3, DDR3L, LPDDR3, and DDR4 Memory Power SuppliesGo

5 Pin Configuration and Functions

RUK Package
20-Pin WQFN
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
DRVH 14 O High-side MOSFET gate driver output.
DRVL 11 O Low-side MOSFET gate driver output.
GND 7 — Signal ground.
MODE 19 I Connect resistor to GND to configure switching frequency, control mode and discharge mode. (See Table 2)
PGND 10 — Gate driver power ground. RDS(on) current sensing input(+).
PGOOD 20 O Powergood signal open drain output. PGOOD goes high when VDDQ output voltage is within the target range.
REFIN 8 I Reference input for VDDQ. Connect to the midpoint of a resistor divider from VREF to GND. Add a capacitor for stable operation.
SW 13 I/O High-side MOSFET gate driver return. RDS(on) current sensing input(–).
S3 17 I S3 signal input. (See Table 1)
S5 16 I S5 signal input. (See Table 1)
TRIP 18 I Connect resistor to GND to set OCL at VTRIP/8. Output 10-μA current at room temperature, TC = 4700 ppm/°C.
VBST 15 I High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from the VBST pin to the SW pin.
VDDQSNS 9 I VDDQ output voltage feedback. Reference input for VTTREF. Also serves as power supply for VTTREF.
VLDOIN 2 I Power supply input for VTT LDO. Connect VDDQ in typical application.
VREF 6 O 1.8-V reference output
VTT 3 O VTT 2-A LDO output. Need to connect 10 μF or larger capacitance for stability.
VTTGND 4 — Power ground for VTT LDO
VTTREF 5 O Buffered VTT reference output. Need to connect 0.22 μF or larger capacitance for stability.
VTTSNS 1 I VTT output voltage feedback.
V5IN 12 I 5-V power supply input for internal circuits and MOSFET gate drivers.
Thermal pad — — Thermal pad. Connect directly to system GND plane with multiple vias.

 
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