SLUSAE1F December   2010  – December 2018 TPS51916

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VDDQ Switch Mode Power Supply Control
      2. 7.3.2  VREF and REFIN, VDDQ Output Voltage
      3. 7.3.3  Soft-Start and Powergood
      4. 7.3.4  Power State Control
      5. 7.3.5  Discharge Control
      6. 7.3.6  VTT and VTTREF
      7. 7.3.7  VDDQ Overvoltage and Undervoltage Protection
      8. 7.3.8  VDDQ Out-of-Bound Operation
      9. 7.3.9  VDDQ Overcurrent Protection
      10. 7.3.10 VTT Overcurrent Protection
      11. 7.3.11 V5IN Undervoltage Lockout Protection
      12. 7.3.12 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE Pin Configuration
      2. 7.4.2 D-CAP™ Mode
    5. 7.5 D-CAP2™ Mode Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 DDR3, D-CAP™ 400-kHz Application with Tracking Discharge
        1. 8.1.1.1 Design Requirements
        2. 8.1.1.2 Detailed Design Procedure
          1. 8.1.1.2.1 1. Determine the value of R1 AND R2
          2. 8.1.1.2.2 2. Choose the inductor
          3. 8.1.1.2.3 3. Choose the OCL setting resistance, RTRIP
          4. 8.1.1.2.4 Choose the output capacitors
        3. 8.1.1.3 Application Curves
      2. 8.1.2 DDR3, DCAP-2 500-kHz Application, with Tracking Discharge
        1. 8.1.2.1 Design Requirements
        2. 8.1.2.2 Detailed Design Procedure
          1. 8.1.2.2.1 Select Mode and Switching Frequency
          2. 8.1.2.2.2 Determine output capacitance
        3. 8.1.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.2 D-CAP™ Mode

Figure 36 shows a simplified model of D-CAP™ mode architecture.

TPS51916 v10136_lusab9.gifFigure 36. Simplified D-CAP™ Model

The VDDQSNS voltage is compared with REFIN voltage. The PWM comparator creates a set signal to turn on the high-side MOSFET. The gain and speed of the comparator is high enough to maintain the voltage at the beginning of each on-cycle (or the end of each off-cycle) to be substantially constant. The DC output voltage monitored at VDDQ may have line regulation due to ripple amplitude that slightly increases as the input voltage increase. The D-CAP™ mode offers flexibility on output inductance and capacitance selections with ease-of-use without complex feedback loop calculation and external components. However, it does require a sufficient level of ESR that represents inductor current information for stable operation and good jitter performance. Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended.

The requirement for loop stability is simple and is described in Equation 3. The 0-dB frequency, f0 defined in Equation 3, is recommended to be lower than 1/3 of the switching frequency to secure proper phase margin.

Equation 3. TPS51916 q_f0_lusab9.gif

where

  • ESR is the effective series resistance of the output capacitor
  • COUT is the capacitance of the output capacitor
  • fsw is switching frequency

Jitter is another attribute caused by signal-to-noise ratio of the feedback signal. One of the major factors that determine jitter performance in D-CAP™ mode is the down-slope angle of the VDDQSNS ripple voltage. Figure 37 shows, in the same noise condition, that jitter is improved by making the slope angle larger.

TPS51916 v10139_lusab9.gifFigure 37. Ripple Voltage Slope and Jitter Performance

For a good jitter performance, use the recommended down slope of approximately 20 mV per switching period as shown in Figure 37 and Equation 4.

Equation 4. TPS51916 q_jitter_lusab9.gif

where

  • VOUT is the VDDQ output voltage
  • LX is the inductance