SLVSBF1A May   2012  – February 2019 TPS53014

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Operation
      2. 7.3.2 Auto-Skip Eco-Mode Control
      3. 7.3.3 Drivers
      4. 7.3.4 5-Volt Regulator
      5. 7.3.5 Soft Start and Pre-Biased Soft Start
      6. 7.3.6 Overcurrent Protection
      7. 7.3.7 Over/Undervoltage Protection
      8. 7.3.8 UVLO Protection
      9. 7.3.9 Thermal Shutdown
  8. 8 Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Detailed Design Procedure
        1. 8.1.1.1 Component Selection
          1. 8.1.1.1.1 Inductor
          2. 8.1.1.1.2 Output Capacitor
          3. 8.1.1.1.3 Input Capacitor
          4. 8.1.1.1.4 Bootstrap Capacitor
          5. 8.1.1.1.5 VREG5 Capacitor
          6. 8.1.1.1.6 Choose Output Voltage Resistors
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Community Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DGS Package
10-Pin VSSOP
Top View
TPS53014 pinout_slvsbf1.gif

Pin Functions

PIN I/O DESCRIPTION
NAME VSSOP-10
VFB 1 I D-CAP2 feedback input. Connect to output voltage with resistor divider.
SS 2 O Soft start programming pin. Connect capacitor from SS pin to GND to program soft start time.
VREG5 3 O Output of 5-V linear regulator and supply for MOSFET driver. Bypass to GND with a minimum 4.7-μF high quality ceramic capacitor. VREG5 is active when EN is asserted high.
EN 4 I Enable. Pull High to enable converter.
VIN 5 I Supply Input for 5-V linear regulator. Bypass to GND with a minimum 0.1-μF high quality ceramic capacitor.
PGND 6 I System ground.
DRVL 7 O Low-side N-Channel MOSFET gate driver output. PGND referenced driver switches between PGND(OFF) and VREG5(ON).
SW 8 I/O Switch node connections for both the high-side driver and over current comparator.
DRVH 9 O High-side N-channel MOSFET gate driver output. SW referenced driver switches between SW(OFF) and VBST(ON).
VBST 10 I High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from VBST to SW. An internal diode is connected between VREG5 and VBST