SLVSA93A March   2010  – August 2014 TPS53127

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  PWM Operation
      2. 8.3.2  Drivers
      3. 8.3.3  PWM Frequency and Adaptive On-Time Control
      4. 8.3.4  5-Volt Regulator
      5. 8.3.5  Soft Start
      6. 8.3.6  Pre-Bias Support
      7. 8.3.7  Output Discharge Control
      8. 8.3.8  Over Current Limit
      9. 8.3.9  Over/Under Voltage Protection
      10. 8.3.10 UVLO Protection
      11. 8.3.11 Thermal Shutdown
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application, QFN
      1. 9.2.1 Design Requirements (QFN)
      2. 9.2.2 Detailed Design Procedure (QFN)
        1. 9.2.2.1 Choose Inductor
        2. 9.2.2.2 Choose Output Capacitor
        3. 9.2.2.3 Choose Input Capacitor
        4. 9.2.2.4 Choose Bootstrap Capacitor
        5. 9.2.2.5 Choose VREG5 and V5FILT Capacitor
        6. 9.2.2.6 Choose Output Voltage Set Point Resistors
        7. 9.2.2.7 Choose Over Current Set Point Resistor
        8. 9.2.2.8 Choose Soft Start Capacitor
      3. 9.2.3 Application Curves (QFN)
    3. 9.3 Typical Application Circuit, TSSOP
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

9.1 Application Information

9.2 Typical Application, QFN

The TPS53127 is a Dual D-CAP2™ Mode Control Step-Down Controller in a realistic cost-sensitive application. Providing both a low core-type 1.05 V and I/O type 1.8 V output from a loosely regulated 12 V source. Idea applications are: Digital TV Power Supply, Networking Home Pin, Digital Set-Top Box (STB), DVD Player/Recorder, and Gaming Consoles.

typ_app_lvsa93.gifFigure 12. Typical Application Circuit

9.2.1 Design Requirements (QFN)

Table 1. Design Parameters

PARAMETERS EXAMPLE VALUES
Input voltage 12 V
Output voltage VO1 = 1.8 V, VO2 = 1.05 V

9.2.2 Detailed Design Procedure (QFN)

9.2.2.1 Choose Inductor

The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load. Larger ripple current increases output ripple voltage, improve S/N ratio and contribute to stable operation.

Equation 3 can be used to calculate L1.

Equation 3. eq3a_lvs947.gif

The inductors current ratings needs to support both the RMS (thermal) current and the Peak (saturation) current. The RMS and peak inductor current can be estimated as follows.

Equation 4. eq4a_lvs947.gif
Equation 5. eq5a_lvs947.gif
Equation 6. eq6a_lvs947.gif

Note: The calculation above shall serve as a general reference. To further improve transient response, the output inductance could be reduced further. This needs to be considered along with the selection of the output capacitor.

9.2.2.2 Choose Output Capacitor

The capacitor value and ESR determines the amount of output voltage ripple and load transient response. it is recommended to use a ceramic output capacitor.

Equation 7. eq7a_lvs947.gif
Equation 8. eq8a_lvs947.gif
Equation 9. eq9b_lvs947.gif

Where

Equation 10. eq10a_lvs947.gif

Select the capacitance value greater than the largest value calculated from Equation 7, Equation 8 and Equation 9. The capacitance for C1 should be greater than 66 μF.

Where

  • ΔVOS = The allowable amount of overshoot voltage in load transition.
  • ΔVUS = The allowable amount of undershoot voltage in load transition.
  • tmin(off) = Minimum off time

9.2.2.3 Choose Input Capacitor

The TPS53127 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A minimum 10-μF high-quality ceramic capacitor is recommended for the input capacitor. The capacitor voltage rating needs to be greater than the maximum input voltage.

9.2.2.4 Choose Bootstrap Capacitor

The TPS53127 requires a bootstrap capacitor from SW to VBST to provide the floating supply for the high-side drivers. A minimum 0.1-μF high-quality ceramic capacitor is recommended. The voltage rating should be greater than 10 V.

9.2.2.5 Choose VREG5 and V5FILT Capacitor

The TPS53127 requires both the VREG5 regulator and V5FILT input are bypassed. A minimum 4.7-μF high-quality ceramic capacitor must be connected between the VREG5 and GND for proper operation. A minimum 1-μF high-quality ceramic capacitor must be connected between the V5FILT and GND for proper operation. Both of these capacitors’ voltage ratings should be greater than 10 V.

9.2.2.6 Choose Output Voltage Set Point Resistors

The output voltage is set with a resistor divider from the output voltage node to the VFBx pin. It is recommended to use 1% tolerance or better resisters. Select R2 between 10 kΩ and 100 kΩ and use Equation 11 or Equation 12 to calculate R1.

Equation 11. eq_11_lvsa93.gif
Equation 12. eq11a1_lvs947.gif

Where

VFB(RIPPLE) = Ripple voltage at VFB

Vswinj = Ripple voltage at error comparator

9.2.2.7 Choose Over Current Set Point Resistor

Equation 13. eq12a_lvs947.gif
Equation 14. eq13a_lvs947.gif

Where:

  • RDS(ON) = Low side FET on-resistance
  • ITRIP(min) = TRIP pin source current （8.5 μA）
  • VOCL0ff = Minimum over current limit offset voltage (–20 mV)
  • IOCL = Over current limit

9.2.2.8 Choose Soft Start Capacitor

Soft start time equation is as follows.

Equation 15. eq14_lvs947.gif

9.2.3 Application Curves (QFN)

fsw_io1_lvsa93.gif
Figure 13. Switching Frequency (VIN = 12 V) vs Output current (CH1)
fsw_io2a_lvsa93.gif
Figure 14. Switching Frequency (VIN = 12 V) vs Output Current (CH2)
vo_io_lvsa93.gif
Figure 15. Output Voltage (VIN = 12 V) vs Output Current (CH1)
vo_vi1_lvsa93.gif
Figure 17. Output Voltage (VIN = 12 V) vs Input Voltage (CH1)
load1_lvsa93.gif
Figure 19. Load Transient Response
strtup_lvsa93.gif
Figure 21. Start-Up Waveforms
eff18_lvsa93.gif
Figure 23. 1.8 V Efficiency vs Output Current (CH1)
rippple18_lvsa93.gif
Figure 25. 1.8-V Output Ripple Voltage
vo_io2_lvsa93.gif
Figure 16. Output Voltage (VIN = 12 V) vs Output Current (CH2)
vo_vi2_lvsa93.gif
Figure 18. Output Voltage (VIN = 12 V) vs Input Voltage (CH2)
load2_lvsa93.gif
Figure 20. Load Transient Response
strtup2_lvsa93.gif
Figure 22. Start-Up Waveforms
eff105_lvsa93.gif
Figure 24. 1.05 V Efficiency vs Output Current (CH2)
rippple105_lvsa93.gif
Figure 26. 1.05-V Output Ripple Voltage

9.3 Typical Application Circuit, TSSOP

The TPS53127is a Dual D-CAP2™ Mode Control Step-Down Controller in a realistic cost-sensitive application. Providing both a low core-type 1.05 V and I/O type 1.8V output from a loosely regulated 12 V source.

tssop_app_lvsa93.gifFigure 27. Typical Application Circuit

9.3.1 Design Requirements

For the Design Requirements, refer to Design Requirements (QFN).

9.3.2 Detailed Design Procedure

For the Detailed Design Procedure, refer to Detailed Design Procedure (QFN).

9.3.3 Application Curves

For the Application Curves, refer to Application Curves (QFN).