SLVSA93A March   2010  – August 2014 TPS53127

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  PWM Operation
      2. 8.3.2  Drivers
      3. 8.3.3  PWM Frequency and Adaptive On-Time Control
      4. 8.3.4  5-Volt Regulator
      5. 8.3.5  Soft Start
      6. 8.3.6  Pre-Bias Support
      7. 8.3.7  Output Discharge Control
      8. 8.3.8  Over Current Limit
      9. 8.3.9  Over/Under Voltage Protection
      10. 8.3.10 UVLO Protection
      11. 8.3.11 Thermal Shutdown
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application, QFN
      1. 9.2.1 Design Requirements (QFN)
      2. 9.2.2 Detailed Design Procedure (QFN)
        1. 9.2.2.1 Choose Inductor
        2. 9.2.2.2 Choose Output Capacitor
        3. 9.2.2.3 Choose Input Capacitor
        4. 9.2.2.4 Choose Bootstrap Capacitor
        5. 9.2.2.5 Choose VREG5 and V5FILT Capacitor
        6. 9.2.2.6 Choose Output Voltage Set Point Resistors
        7. 9.2.2.7 Choose Over Current Set Point Resistor
        8. 9.2.2.8 Choose Soft Start Capacitor
      3. 9.2.3 Application Curves (QFN)
    3. 9.3 Typical Application Circuit, TSSOP
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

  • Keep the input switching current loop as small as possible. (VIN ≥ C3 ≥ PNGD ≥ Sync FET ≥ SW ≥ Control FET)
  • Place the input capacitor (C3) close to the top switching FET. The output current loop should also be kept as small as possible.
  • Keep the SW node as physically small and short as possible as to minimize parasitic capacitance and inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the feedback terminal (FBx) of the device.
  • Keep analog and non-switching components away from switching components.
  • Make a single point connection from the signal ground to power ground.(1)
  • Do not allow switching current to flow under the device.
  • DRVH and DRVL line should not run close to SW node or minimize it. (2)
  • GND terminals for capacitors of SSx and V5FILT and resistors of feedback and TRIPx should be connected to SGND. (3)
  • GND terminals for capacitors of VREG5 and VIN should be connected to PGND. (4)
  • Signal lines should not run under/near Output Inductor or minimize it. (5)

11.2 Layout Example

Reference designators shown correspond to the schematic of Figure 28.

layout_ds_a_slvsa93.gifFigure 28. Board Layout