SLUSAU4B DECEMBER   2011  – February 2019 TPS53219A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable and Soft-Start
      2. 7.3.2  Adaptive ON-Time D-CAP Control and Frequency Selection
      3. 7.3.3  Small Signal Model
      4. 7.3.4  Ramp Signal
      5. 7.3.5  Adaptive Zero Crossing
      6. 7.3.6  Output Discharge Control
      7. 7.3.7  Low-Side Driver
      8. 7.3.8  High-Side Driver
      9. 7.3.9  Power Good
      10. 7.3.10 Current Sense and Overcurrent Protection
      11. 7.3.11 Overvoltage and Undervoltage Protection
      12. 7.3.12 UVLO Protection
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Light Load Condition in Auto-Skip Operation
      2. 7.4.2 Forced Continuous Conduction Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application With Power Block
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 External Components Selection
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Application With Ceramic Output Capacitors
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 External Parts Selection With All Ceramic Output Capacitors
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over operating free-air temperature range, VDD = 12 V (Unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IVDD VDD supply current VDD current, TA = 25°C, No Load, VEN = 5 V,
VVFB = 0.630 V		 420 590 µA
IVDDSDN VDD shutdown current VDD current, TA=25°C, No Load, VEN=0 V 10 µA
INTERNAL REFERENCE VOLTAGE
VVFB VFB regulation voltage VFB voltage, CCM condition(1) 600 mV
VVFB VFB regulation voltage TA = 25°C 597 600 603 mV
0°C ≤ TA≤ 85°C 595.2 600 604.8
-40°C ≤ TA≤ 85°C 594 600 606
IVFB VFB input current VVFB = 0.630V, TA = 25°C 0.002 0.2 µA
OUTPUT DRIVERS
RDRVH DRVH resistance Source, IDRVH = –50 mA 1.5 3 Ω
Sink, IDRVH = 50 mA 0.7 1.8
RDRVL DRVL resistance Source, IDRVL = –50 mA 1.0 2.2 Ω
Sink, IDRVL = 50 mA 0.5 1.2
tDEAD Dead time DRVH-off to DRVL-on 7 17 30 ns
DRVL-off to DRVH-on 10 22 35
LDO OUTPUT
VVREG LDO output voltage 0 mA ≤ IVREG ≤ 50 mA 5.76 6.2 6.67 V
IVREG LDO output current(1) Maximum current allowed from LDO 50 mA
VDO LDO drop out voltage VVDD = 4.5 V, IVREG = 50 mA 364 mV
BOOT STRAP SWITCH
VFBST Forward voltage VVREG-VBST, IF = 10 mA, TA = 25°C 0.1 0.2 V
IVBSTLK VBST leakagecurrent VVBST = 23 V, VSW = 17 V, TA = 25°C 0.01 1.5 µA
DUTY AND FREQUENCY CONTROL
tOFF(min) Minimum off-time TA = 25°C 150 260 400 ns
tON(min) Minimum ON-time VIN = 17 V, VOUT = 0.6 V, RRF = 0 Ω to VREG,
TA = 25°C(1) 		35 ns
SOFTSTART
tSS Internal soft-start time 0 V ≤ VOUT ≤ 95%, RMODE = 39 kΩ 0.7 ms
0 V ≤ VOUT ≤ 95%, RMODE = 100kΩ 1.4
0 V ≤ VOUT ≤ 95%, RMODE = 200 kΩ 2.8
0 V ≤ VOUT ≤ 95%, RMODE = 470 kΩ 5.6
POWERGOOD
VTHPG PG threshold PG in from lower 92.5% 96% 98.5%
PG in from higher 108% 111% 114%
PG hysteresis 2.5% 5% 7.8%
RPG PG transistor on-resistance 15 30 50 Ω
tPG(del) PG delay after soft-start 0.8 1 1.2 ms
LOGIC THRESHOLD AND SETTING CONDITIONS
VEN EN voltage threshold enable –40°C ≤ TA≤ 85°C 1.8 V
0°C ≤ TA≤ 85°C 1.7
EN voltage threshold disable 0.5
IEN EN input current VEN = 5 V 1 µA
fSW Switching frequency RRF = 0 Ω to GND, TA = 25°C(2) 200 250 300 kHz
RRF = 187 kΩ to GND, TA = 25°C(2) 250 300 350
RRF = 619 kΩ to GND, TA = 25°C(2) 350 400 450
RRF = Open, TA = 25°C(2) 450 500 550
RRF = 866 kΩ to VREG, TA = 25°C(2) 580 650 720
RRF = 309 kΩ to VREG, TA = 25°C(2) 670 750 820
RRF = 124 kΩ to VREG, TA = 25°C(2) 770 850 930
RRF = 0 Ω to VREG, TA = 25°C(2) 880 970 1070
VO DISCHARGE
IDischg VO discharge current VEN = 0 V, VSW = 0.5 V 5 13 mA
PROTECTION: CURRENT SENSE
ITRIP TRIP source current VTRIP = 1 V, TA = 25°C 9 10 11 µA
TCITRIP TRIP current temp. coef. TA = 25°C(1) 4700 ppm/°C
VTRIP Current limit threshold setting range VTRIP-GND voltage 0.2 3 V
VOCL Current limit threshold VTRIP = 3 V 355 375 395 mV
VTRIP = 1.6 V 185 200 215
VTRIP = 0.2 V 17 25 33
VOCLN Negative current limit threshold VTRIP = 3 V –406 –375 –355 mV
VTRIP = 1.6 V –215 –200 –185
VTRIP = 0.2 V –33 –25 –17
VAZC(adj) Auto zero cross adjustable range Positive 3 15 mV
Negative –15 –3
PROTECTION: UVP AND OVP
VOVP OVP trip threshold voltage OVP detect 115% 120% 125%
tOVP(del) OVP propagation delay time VFB delay with 50-mV overdrive 1 µs
VUVP Output UVP trip threshold voltage UVP detect 65% 70% 75%
tUVP(del) Output UVP propagation delay time 0.8 1 1.2 ms
tUVP(en) Output UVP enable delay time from EN to UVP workable, RMODE = 39 kΩ 2.00 2.55 3 ms
UVLO
VUVVREG VREG UVLO threshold Wake up 4 4.18 4.5 V
Hysteresis 0.25
THERMAL SHUTDOWN
TSDN Thermal shutdown threshold Shutdown temperature(1) 145 °C
Hysteresis(1) 10
(1) Ensured by design. Not production tested.
(2) Not production tested. Test conditions are VIN = 12 V, VOUT = 1.1 V, IOUT = 10 A and using the application circuit shown in Figure 18 and Figure 22.