SLUSAU4B DECEMBER   2011  – February 2019 TPS53219A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable and Soft-Start
      2. 7.3.2  Adaptive ON-Time D-CAP Control and Frequency Selection
      3. 7.3.3  Small Signal Model
      4. 7.3.4  Ramp Signal
      5. 7.3.5  Adaptive Zero Crossing
      6. 7.3.6  Output Discharge Control
      7. 7.3.7  Low-Side Driver
      8. 7.3.8  High-Side Driver
      9. 7.3.9  Power Good
      10. 7.3.10 Current Sense and Overcurrent Protection
      11. 7.3.11 Overvoltage and Undervoltage Protection
      12. 7.3.12 UVLO Protection
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Light Load Condition in Auto-Skip Operation
      2. 7.4.2 Forced Continuous Conduction Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application With Power Block
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 External Components Selection
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Application With Ceramic Output Capacitors
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 External Parts Selection With All Ceramic Output Capacitors
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1 Layout Guidelines

Certain points must be considered before starting a layout work using the TPS53219A.

  • Inductors, VIN capacitors, VOUT capacitors and MOSFETs are the power components and should be placed on one side of the PCB (solder side). Other small signal components should be placed on another side (component side). At least one inner plane should be inserted, connected to power ground, in order to shield and isolate the small signal traces from noisy power lines.
  • All sensitive analog traces and components such as VFB, PGOOD, TRIP, MODE and RF should be placed away from high-voltage switching nodes such as SW, DRVL, DRVH or VBST to avoid coupling. Use internal layers as ground planes and shield feedback trace from power traces and components.
  • The DC–DC converter has several high-current loops. The area of these loops should be minimized in order to suppress generating switching noise.
    • The most important loop to minimize the area of is the path from the VIN capacitors through the high and low-side MOSFETs, and back to the capacitors through ground. Connect the negative node of the VIN capacitors and the source of the low-side MOSFET at ground as close as possible.
    • The second important loop is the path from the low-side MOSFET through inductor and VOUT capacitors, and back to source of the low-side MOSFET through ground. Connect source of the low-side MOSFET and negative node of VOUT capacitors at ground as close as possible.
    • The third important loop is of gate driving system for the low-side MOSFET. To turn on the low-side MOSFET, high current flows from VDRV capacitor through gate driver and the low-side MOSFET, and back to negative node of the capacitor through ground. To turn off the low-side MOSFET, high current flows from gate of the low-side MOSFET through the gate driver and PGND of the device, and back to source of the low-side MOSFET through ground. Connect negative node of VDRV capacitor, source of the low-side MOSFET and PGND of the device at ground as close as possible.
  • Because the TPS53219A controls output voltage referring to voltage across VOUT capacitor, the high-side resistor of the voltage divider should be connected to the positive node of VOUT capacitor at the regulatioin point. The low-side resistor should be connected to the GND (analog ground of the device). The trace　from these resistors to the VFB pin should be short and thin. Place on the component side and avoid vias between these resistors and the device.
  • Connect the overcurrent setting resistors from the TRIP pin to GND and make the connections as close as possible to the device. The trace from TRIP pin to resistor and from resistor to GND should avoid coupling to a high-voltage switching node.
  • Connect the frequency setting resistor from RF pin to GND, or to the PGOOD pin, and make the connections as close as possible to the device. The trace from the RF pin to the resistor and from the resistor to GND should avoid coupling to a high-voltage switching node.
  • Connect all GND (analog ground of the device) trace together and connect to power ground or ground plane with a single via or trace or through a 0-Ω resistor at a quiet point
  • Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be as short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace　ad ) of at least 0.5 mm (20 mils) diameter along this trace.
  • The PCB trace defined as switch node, which connects to source of high-side MOSFET, drain of low-side MOSFET and high-voltage side of the inductor, should be as short and wide as possible.
  • Connect the ripple injection VOUT signal (VOUT side of the C1 capacitor in Figure 22) from the terminal of ceramic output capacitor. The AC-coupling capacitor (C7 in Figure 22 ) can be placed near the device.