SLUSAU4B DECEMBER 2011 – February 2019 TPS53219A
PRODUCTION DATA.
From small-signal loop analysis, a buck converter using D-CAP mode can be simplified as shown in Figure 17.
The output voltage is compared with the internal reference voltage (ramp signal is ignored here for simplicity). The PWM comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the comparator can be assumed high enough to keep the voltage at the beginning of each on cycle substantially constant.
For the loop stability, the 0-dB frequency, ƒ0, defined below must be lower than ¼ of the switching frequency.
According to Equation 2, the loop stability of D-CAP mode modulator is mainly determined by the capacitor chemistry. For example, specialty polymer capacitors (SP-CAP) have an output capacitance on the order of several 100 µF and ESR in range of 10 mΩ. These yields an f0 on the order of 100 kHz or less and a more stable loop. However, ceramic capacitors have an ƒ0 at more than 700 kHz, and require special care when used with this modulator. An application circuit for ceramic capacitor is described in section External Parts Selection With All Ceramic Output Capacitors.