SLUSAS8A December   2011  – October 2016 TPS53313

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Soft-Start Operation
      2. 7.3.2 Power Good
      3. 7.3.3 UVLO Function
      4. 7.3.4 Overcurrent (OC) Protection
      5. 7.3.5 Overvoltage and Undervoltage Protection
      6. 7.3.6 Overtemperature Protection
      7. 7.3.7 Output Discharge
      8. 7.3.8 Switching Frequency Setting and Synchronization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Mode
      2. 7.4.2 Light Load Operation
      3. 7.4.3 Forced Continuous Conduction Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Inductor Selection
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Output Voltage Setting Resistors Selection
        5. 8.2.2.5 Compensation Design
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS53313 device is a high-efficiency synchronous-buck converter. The device suits low output voltage point-of-load applications with 6-A or lower output current in computing and similar digital consumer applications.

8.2 Typical Application

This design example describes a voltage-mode, 6-A synchronous buck converter with integrated MOSFETs. The device provides a fixed 1.2-V output at up to 6-A from a 12-V input bus.

TPS53313 slusas8_typ_schem.gif Figure 13. Typical Application Schematic

8.2.1 Design Requirements

This design example illustrates the design process and component selection for a single-output synchronous buck converter using the TPS53313. The design example schematic of a is shown in Figure 13. The specification of the converter is listed in Table 3.

Table 3. Design Example Converter Specifications

PARAMETER TEST CONDITION MIN TYP MAX UNIT
VIN Input voltage 10.8 12 13.2 V
VOUT Output voltage 1.2 V
VRIPPLE Output ripple IOUT = 6 A 1% of VOUT V
IOUT Output current 6 A
fSW Switching frequency 600 kHz

8.2.2 Detailed Design Procedure

8.2.2.1 Output Inductor Selection

The inductance value should be determined to give the ripple current of approximately 20% to 40% of maximum output current. The inductor ripple current is determined by Equation 1.

Equation 1. TPS53313 q_ilripple_lusas8.gif

The inductor also requires a low DCR to achieve good efficiency, as well as enough room above peak inductor current before saturation.

8.2.2.2 Output Capacitor Selection

The output capacitor selection is determined by output ripple and transient requirement. When operating in CCM, the output ripple has three components:

Equation 2. TPS53313 q_vripple_lusas8.gif
Equation 3. TPS53313 q_vripplec_lusas8.gif
Equation 4. TPS53313 q_vrippleesr_lusas8.gif
Equation 5. TPS53313 q_vrippleesl_lusas8.gif

When ceramic output capacitor is chosen, the ESL component is usually negligible. In the case when multiple output capacitors are used, the total ESR and ESL should be the equivalent of the all output capacitors in parallel.

When operating in DCM, the output ripple is dominated by the component determined by capacitance. It also varies with load current and can be expressed as shown in Equation 6.

Equation 6. TPS53313 q_vrippleedcm_lusas8.gif

where

  • α is the DCM on-time coefficient and can be expressed as shown in Equation 7.
Equation 7. TPS53313 q_alpha_lusas8.gif
TPS53313 v11253_lusas8.gif Figure 14. DCM Output Voltage Ripple

8.2.2.3 Input Capacitor Selection

The selection of input capacitor should be determined by the ripple current requirement. The ripple current generated by the converter needs to be absorbed by the input capacitors as well as the input source. The RMS ripple current from the converter can be expressed as shown in Equation 8.

Equation 8. TPS53313 q_iiripple_lusas8.gif

where

  • D is the duty cycle and can be expressed as shown in Equation 9.
Equation 9. TPS53313 q_d_lusas8.gif

To minimize the ripple current drawn from the input source, sufficient input decoupling capacitors should be placed close to the device. The ceramic capacitor is recommended due to its low ESR and low ESL. The input voltage ripple can be calculated as below when the total input capacitance is determined by Equation 10.

Equation 10. TPS53313 q_vinripple_lusas8.gif

8.2.2.4 Output Voltage Setting Resistors Selection

The output voltage is programmed by the voltage-divider resistor, R1 and R2 shown in Equation 11. R1 is connected between VFB pin and the output, and R2 is connected between the VFB pin and GND. Recommended value for R1 is from 1k to 5k. Determine R2 using Equation 11.

Equation 11. TPS53313 q_r2_lusas8.gif

8.2.2.5 Compensation Design

The TPS53313 employs voltage mode control. To effectively compensate the power stage and ensure fast transient response, Type III compensation is typically used.

Equation 12. TPS53313 q_gco_lusas8.gif

The output LC filter introduces a double pole which can be calculated as shown in Equation 13.

Equation 13. TPS53313 q_fdp_lusas8.gif

The ESR zero of can be calculated as shown in Equation 14.

Equation 14. TPS53313 q_fesr_lusas8.gif

Figure 15 and Figure 16 shows the configuration of Type III compensation and typical pole and zero locations. Equation 15 through Equation 17 describe the compensator transfer function and poles and zeros of the Type III network.

Equation 15. TPS53313 q_gea_lusas8.gif
Equation 16. TPS53313 q_fz1_lusas8.gif
Equation 17. TPS53313 q_fz2_lusas8.gif
TPS53313 v11258_lusas8.gif Figure 15. Type III Compensation
Network Schematic
TPS53313 v11257_lusas8.gif Figure 16. Type III Compensation
Network Waveform
Equation 18. TPS53313 q_fp1_lusas8.gif
Equation 19. TPS53313 q_fp2_lusas8.gif
Equation 20. TPS53313 q_fp3_lusas8.gif

The two zeros can be placed near the double pole frequency to cancel the response from the double pole. One pole can be used to cancel ESR zero, and the other non-zero pole can be placed at half switching frequency to attenuate the high frequency noise and switching ripple. Suitable values can be selected to achieve a compromise between high phase margin and fast response. A phase margin higher than 45° is required for stable operation.

For DCM operation, a capacitor with a value between 100 pF and 220 pF is recommended for C3 when the output capacitance is between 22 µF and 220 µF.

8.2.3 Application Curves

TPS53313 fig4_luu819.gif Figure 17. Efficiency
TPS53313 fig6_luu819.gif
Figure 19. Line Regulation
TPS53313 fig8_luu819.gif
12-V VIN, 1.2-V VOUT, fSW = 600 kHz
Figure 21. Output Load, 0-A to 3-A Transient
Under Skip Mode
TPS53313 fig14_luu819.gif
12-V VIN, 1.2-V VOUT, 0-A IOUT, 1-ms SS
Figure 23. Pre-bias Start-Up Waveform
TPS53313 fig16_luu819.gif
12-V VIN, 1.2-V VOUT, IOUT increases from 6 A to 7.8 A
Figure 25. Overcurrent Protection Waveform
TPS53313 fig5_luu819.gif Figure 18. Load Regulation
TPS53313 fig7_luu819.gif
12-V VIN, 1.2-V VOUT, fSW = 600 kHz
Figure 20. Output Load, 0-A to 3-A Transient
Under FCCM Mode
TPS53313 fig13_luu819.gif
12-V VIN, 1.2-V VOUT, 6-A IOUT, 1-ms SS
Figure 22. Start-Up Waveform
TPS53313 fig15_luu819.gif
12-V VIN, 1.2-V VOUT, 0-A IOUT
Figure 24. Shut-Down Waveform