SLUSAS8A December   2011  – October 2016 TPS53313

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Soft-Start Operation
      2. 7.3.2 Power Good
      3. 7.3.3 UVLO Function
      4. 7.3.4 Overcurrent (OC) Protection
      5. 7.3.5 Overvoltage and Undervoltage Protection
      6. 7.3.6 Overtemperature Protection
      7. 7.3.7 Output Discharge
      8. 7.3.8 Switching Frequency Setting and Synchronization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Mode
      2. 7.4.2 Light Load Operation
      3. 7.4.3 Forced Continuous Conduction Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Inductor Selection
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Output Voltage Setting Resistors Selection
        5. 8.2.2.5 Compensation Design
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RGE Package
24-Pin VQFN
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NO. NAME
1 EN I Enable pin
2 PG O Power good output flag. Open drain output. Pull up to an external rail through a resistor.
3 VIN P Gate driver supply and power conversion voltage
4 VIN P Gate driver supply and power conversion voltage
5 VIN P Gate driver supply and power conversion voltage
6 VIN P Gate driver supply and power conversion voltage
7 PGND P Device power ground terminal
8 PGND P Device power ground terminal
9 PGND P Device power ground terminal
10 PGND P Device power ground terminal
11 PGND P Device power ground terminal
12 PGND P Device power ground terminal
13 SW O Output inductor connection to integrated power devices
14 SW O Output inductor connection to integrated power devices
15 SW O Output inductor connection to integrated power devices
16 SW O Output inductor connection to integrated power devices
17 VBST P Supply input for high-side MOSFET (bootstrap terminal). Connect capacitor from this pin to SW terminal.
18 BP7 P Bias for internal circuitry and driver
19 BP3 P Input bias supply for analog functions
20 AGND G Device analog ground terminal
21 RT/SYNC I/O Synchronized to external clock. Program the switching frequency by connecting with a resistor to GND.
22 MODE/SS I Mode configuration pin. Connect with a resistor to GND sets different modes and soft-start time, parallel a capacitor (or no capacitor) with the resistor changes the current limit threshold. Shorting MODE/SS pin to supply inhibits the device; shorting MODE/SS pin to AGND is equivalent to 10-kΩ resistor setting is not recommended (see Table 1 and Table 2 for resistor and capacitor settings).
23 COMP O Error amplifier compensation terminal. Type III compensation method is generally recommended for stability.
24 FB I Voltage feedback pin. Use for OVP, UVP, and power good determination
(1) B = Bidirectional, G = Ground, I = Input, O = Output, P = Supply