The TPS53317A device is a FET-integrated synchronous buck regulator designed mainly for DDR termination. It can provide a regulated output at ½ VDDQ with both sink and source capability. The TPS53317A device employs D-CAP+ mode operation that provides ease of use, low external component count and fast transient response. The device can also be used for other point-of-load (POL) regulation applications requiring up to 6 A. In addition, the device supports full, 6-A, output sinking current capability with tight voltage regulation.
The device features two switching frequency settings (600 kHz and 1 MHz), integrated droop support, external tracking capability, pre-bias startup, output soft discharge, integrated bootstrap switch, power good function, V5IN pin UVLO protection, and supports both ceramic and SP/POSCAP capacitors. It supports input voltages up to 6.0 V, and output voltages adjustable from 0.45 V to 2.0 V.
The TPS53317A device is available in the 3.5 mm × 4 mm, 20-pin, VQFN package (Green RoHs compliant and Pb free) with TI proprietary Integrated MOSFET and packaging technology and is specified from –40°C to 85°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS53317A | VQFN (20) | 3.50 mm × 4.00 mm |
Changes from * Revision (November 2015) to A Revision
PIN | I/O(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
BST | 16 | I | Power supply for internal high-side gate driver. Connect a 0.1-µF bootstrap capacitor between this pin and the SW pin. Include a series boot resistor when the voltage spike on switching node is above 7 V. |
COMP | 8 | O | Connect an R-C-C network between this pin and VREF for loop compensation. |
EN | 17 | I | Enable pin (3.3-V logic compatible). |
GND | 6 | – | Analog ground. |
MODE | 18 | I | Allows selection of different operation modes. (See Table 1) |
PGND | 1 | G | Power ground. |
2 | |||
3 | |||
PGOOD | 19 | O | Open drain power good output. Connect pullup resistor. |
REFIN | 9 | I | External tracking reference input. Apply voltage between 0.45 V to 2.0 V. For non-tracking mode, connect REFIN to VREF via resistor divider. |
SW | 11 | I/O | Switching node output. |
12 | |||
13 | |||
14 | |||
15 | |||
V5IN | 20 | I | 5-V power supply for analog circuits and gate drive. |
VIN | 4 | I | Power supply input pin. |
5 | |||
VOUT | 10 | I | Output voltage monitor input pin. |
VREF | 7 | O | 2.0-V reference output. Connect a ceramic capacitor with a value of 0.22-µF or greater between this pin and GND. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltage range | BST (with respect to SW), V5IN, VIN | –0.3 | 7 | V |
BST | –0.3 | 14 | ||
EN | –0.3 | 7 | ||
MODE, REFIN | –0.3 | 3.6 | ||
VOUT | –1 | 3.6 | ||
Output voltage range | SW | –2 | 7 | V |
SW (transient 20 ns and E = 5 µJ) | –3 | |||
COMP, VREF | –0.3 | 3.6 | ||
PGOOD | –0.3 | 7 | ||
PGND | –0.3 | 0.3 | ||
Operating junction temperature, TJ | –40 | 150 | ˚C | |
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds | 300 | ˚C | ||
Storage temperature, Tstg | –55 | 150 | ˚C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Input voltage range | BST (with respect to SW), EN, VIN | –0.1 | 6.5 | V | |
V5IN | 4.5 | 6.5 | |||
BST | –0.1 | 13.5 | |||
SW | –1.0 | 6.5 | |||
VOUT, MODE, REFIN | –0.1 | 3.5 | |||
Output voltage range | COMP | –0.1 | 3.5 | V | |
VREF | 2 | ||||
PGOOD | –0.1 | 6.5 | |||
PGND | –0.1 | 0.1 | |||
Operating temperature range, TA | -40 | 85 | °C |
THERMAL METRIC(1) | TPS53317A | UNIT | |
---|---|---|---|
RGB (VQFN) | |||
20 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 35.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 39.6 | °C/W |
RθJB | Junction-to-board thermal resistance | 12.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.5 | °C/W |
ψJB | Junction-to-board characterization parameter | 12.5 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 3.7 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY: VOLTAGE, CURRENTS AND 5-V UVLO | ||||||
IVINSD | VIN shutdown current | EN = 'LO' | 0.02 | 5 | µA | |
VV5IN | V5IN supply voltage | V5IN voltage range | 4.5 | 5.0 | 6.5 | V |
IV5IN | V5IN supply current | EN =’HI’, V5IN supply current, fSW = 600 kHz | 1.1 | 2 | mA | |
IV5INSD | V5IN shutdown current | EN = ‘LO’, V5IN shutdown current | 0.2 | 7.0 | µA | |
VV5UVLO | V5IN UVLO | Ramp up; EN = 'HI' | 4.20 | 4.37 | 4.50 | V |
VV5UVHYS | V5IN UVLO hysteresis | Falling hysteresis | 440 | mV | ||
VVREFUVLO | REF UVLO(1) | Rising edge of VREF, EN = 'HI' | 1.8 | V | ||
VVREFUVHYS | REF UVLO hysteresis(1) | 100 | mV | |||
VPOR5VFILT | Reset | OVP latch is reset by V5IN falling below the reset threshold | 1.5 | 2.3 | 3.1 | V |
VOLTAGE FEEDBACK LOOP: VREF, VOUT, AND VOLTAGE GM AMPLIFIER | ||||||
VOUTTOL | Output voltage accuracy | VREFIN = 1 V, No droop | –1% | 0% | 1% | |
VREFIN = 0.6 V, No droop | –1% | 0% | 1% | |||
VVREF | VREF | IVREF = 0 µA | 1.98 | 2.00 | 2.02 | V |
IVREF = 50 µA | 1.975 | 2.000 | 2.025 | |||
IREFSNK | VREF sink current | VVREF = 2.05 V | 2.5 | mA | ||
gM | Transconductance | 1.00 | mS | |||
VCM | Common mode input voltage range(1) | 0 | 2 | V | ||
VDM | Differential mode input voltage | 0 | 80 | mV | ||
ICOMPSNK | COMP pin maximum sinking current | VCOMP = 2 V, (VREFIN – VOUT) = 80 mV | 80 | µA | ||
ICOMPSRC | COMP pin maximum sourcing current | VCOMP = 2 V | -80 | µA | ||
VOFFSET | Input offset voltage | TA = 25°C | 0 | mV | ||
RDSCH | Output voltage discharge resistance | 42 | Ω | |||
f–3dbVL | –3dB Frequency(1) | 4.5 | 6.0 | 7.5 | MHz | |
CURRENT SENSE: CURRENT SENSE AMPLIFIER, OVERCURRENT AND ZERO CROSSING | ||||||
ACSINT | Internal current sense gain | Gain from the current of the low-side FET to PWM comparator when PWM = "OFF" | 43 | 53 | 57 | mV/A |
IOCL | Positive overcurrent limit (valley) | 7.6 | A | |||
IOCL(neg) | Negative overcurrent limit (valley) | –9.3 | A | |||
VZXOFF | Zero crossing comp internal offset | 0 | mV | |||
PROTECTION: OVP, UVP, PGOOD, and THERMAL SHUTDOWN | ||||||
VPGDLL | PGOOD deassert to lower (PGOOD → Low) |
Measured at the VOUT pin wrt/ VREFIN | 84% | |||
VPGHYSHL | PGOOD high hysteresis | 8% | ||||
VPGDLH | PGOOD de-assert to higher (PGOOD → Low) |
Measured at the VOUT pin wrt/ VREFIN | 116% | |||
VPGHYSHH | PGOOD high hysteresis | -8% | ||||
VINMINPG | Minimum VIN voltage for valid PGOOD | Measured at the VIN pin with a 2-mA sink current on PGOOD pin. V5IN is grounded here.(3) | 0.9 | 1.3 | 1.5 | V |
VOVP | OVP threshold | Measured at the VOUT pin wrt/ VREFIN, VREFIN = 1 V | 117% | 120% | 123% | |
VUVP | UVP threshold | Measured at the VOUT pin wrt/ VREFIN, device latches OFF, begins soft-stop, VREFIN = 1 V | 65% | 68% | 71% | |
THSD | Thermal shutdown(1) | Latch off controller, attempt soft-stop. | 145 | °C | ||
THSD(hys) | Thermal Shutdown hysteresis(1) | Controller re-starts after temperature has dropped | 10 | °C | ||
DRIVERS: BOOT STRAP SWITCH | ||||||
RDSONBST | Internal BST switch on-resistance | IBST = 10 mA, TA = 25°C | 10 | Ω | ||
IBSTLK | Internal BST switch leakage current | VBST = 14 V, VSW = 7 V | 1 | µA | ||
TIMERS: ON-TIME, MINIMUM OFF-TIME, SS, AND I/O TIMINGS | ||||||
tONESHOTC | PWM one-shot(1) | VVIN = 5 V, VVOUT = 1.05 V, fSW = 1 MHz | 210 | ns | ||
VVIN = 5 V, VVOUT = 1.05 V, fSW = 600 kHz | 310 | |||||
tMIN(off) | Minimum OFF time | VVIN = 5 V, VVOUT = 1.05 V, fSW = 1 MHz, DRVL on, SW = PGND, VVOUT < VREFIN |
270 | ns | ||
tINT(SS) | Soft-start time | From VOUT ramp starting to VOUT =95%, default setting | 1.6 | ms | ||
tINT(SSDLY) | Internal soft-start delay time | From VVREF = 2 V to VOUT is ready to ramp up | 260 | µs | ||
tPGDDLY | PGOOD startup delay time | At external tracking, the time from VOUT is ready to ramp up | 8 | ms | ||
tPGDPDLYH | PGOOD high propagation delay time | 50 mV over drive, rising edge | 0.8 | 1 | 1.2 | ms |
tPGDPDLYL | PGOOD low propagation delay time | 50 mV over drive, falling edge | 10 | µs | ||
tOVPDLY | OVP delay time | Time from the VOUT pin out of +20% of REFIN to OVP fault | 10 | µs | ||
tUVDLYEN | Undervoltage fault enable delay | Time from EN_INT going high to undervoltage fault is ready | 2 | ms | ||
External tracking from VOUT ramp starts | 8 | |||||
tUVPDLY | UVP delay time | Time from the VOUT pin out of –32% of REFIN to UVP fault | 256 | µs | ||
LOGIC PINS: I/O VOLTAGE AND CURRENT | ||||||
PGOOD pull-down voltage | PGOOD low impedance, ISINK = 4 mA, VV5IN = 4.5 V | 0.3 | V | |||
PGOOD leakage current | PGOOD high impedance, forced to 5.5 V | –1 | 0 | 1 | µA | |
EN logic high | EN, VCCP logic | 2 | V | |||
EN logic low | EN, VCCP logic | 0.5 | V | |||
EN input current | 1 | µA | ||||
MODE threshold voltage(2) | Threshold 1 | 80 | 130 | 180 | mV | |
Threshold 2 | 200 | 250 | 300 | |||
Threshold 3 | 370 | 420 | 470 | |||
Threshold 4 | 550 | 600 | 650 | |||
Threshold 5 | 830 | 880 | 930 | |||
Threshold 6 | 1200 | 1250 | 1300 | |||
Threshold 7 | 1765 | 1800 | 1850 | |||
MODE current | 15 | µA |
VIN = 1.5 V | VOUT = 0.75 V |
VIN = 1.5 V | VOUT = 0.75 V |
TA = 25°C | IOUT = 2 A |