SLUSAE5G August   2011  – April 2021 TPS53355

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings (1)
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Infomation
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 5-V LDO and VREG Start-Up
      2. 7.3.2 Adaptive On-Time D-CAP Control and Frequency Selection
      3. 7.3.3 Ramp Signal
      4. 7.3.4 Adaptive Zero Crossing
      5. 7.3.5 Power-Good
      6. 7.3.6 Current Sense, Overcurrent and Short Circuit Protection
      7. 7.3.7 Overvoltage and Undervoltage Protection
      8. 7.3.8 UVLO Protection
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable, Soft Start, and Mode Selection
      2. 7.4.2 Auto-Skip Eco-mode™ Light Load Operation
      3. 7.4.3 Forced Continuous Conduction Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Small Signal Model
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application Circuit Diagram with Ceramic Output Capacitors
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 External Component Selection
          3. 8.2.1.2.3 External Component Selection Using All Ceramic Output Capacitors
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Application Circuit
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 External Component Selection
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DQP|22
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-E2938A36-A1C5-4B12-86BF-AA636F414F07-low.gif
N/C = no connection
Figure 5-1 Package With PowerPad22-Pins (LSON-CLIP)Top View
Table 5-1 Pin Functions
PIN I/O/P(1) DESCRIPTION
NAME NO
EN 2 I Enable pin. Typical turn-on threshold voltage is 1.2 V. Typical turn-off threshold is 0.95 V.
GND — — Ground and thermal pad of the device. Use proper number of vias to connect to ground plane.
LL 6 B Output of converted power. Connect this pin to the output Inductor.
7
8
9
10
11
MODE 20 I Soft-start and Skip/CCM selection. Connect a resistor to select soft-start time using Table 7-3. The soft-start time is detected and stored into internal register during start-up.
N/C 5 No connect.
PGOOD 3 O Open drain power good flag. Provides 1-ms start-up delay after VFB falls in specified limits. When VFB goes out of the specified limits PGOOD goes low after a 2-µs delay.
RF 22 I Switching frequency selection. Connect a resistor to GND or VREG to select switching frequency using Table 7-1. The switching frequency is detected and stored during the startup.
TRIP 21 I OCL detection threshold setting pin. ITRIP = 10 µA at room temperature, 4700 ppm/°C current is sourced and set the OCL trip voltage as follows:
VOCL = VTRIP/32 (VTRIP ≤ 2.4 V, VOCL ≤ 75 mV)
VBST 4 P Supply input for high-side FET gate driver (boost terminal). Connect capacitor from this pin to LL node. Internally connected to VREG via bootstrap MOSFET switch.
VDD 19 P Controller power supply input. VDD input voltage range is from 4.5 V to 25 V.
VFB 1 I Output feedback input. Connect this pin to Vout through a resistor divider.
VIN 12 P Conversion power input. VIN input voltage range is from 1.5 V to 15 V.
13
14
15
16
17
VREG 18 P 5-V low drop out (LDO) output. Supplies the internal analog circuitry and driver circuitry.
(1) I=Input, O=Output, B=Bidirectional, P=Supply