SLUSAE5G August   2011  – April 2021 TPS53355

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings (1)
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Infomation
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 5-V LDO and VREG Start-Up
      2. 7.3.2 Adaptive On-Time D-CAP Control and Frequency Selection
      3. 7.3.3 Ramp Signal
      4. 7.3.4 Adaptive Zero Crossing
      5. 7.3.5 Power-Good
      6. 7.3.6 Current Sense, Overcurrent and Short Circuit Protection
      7. 7.3.7 Overvoltage and Undervoltage Protection
      8. 7.3.8 UVLO Protection
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable, Soft Start, and Mode Selection
      2. 7.4.2 Auto-Skip Eco-mode™ Light Load Operation
      3. 7.4.3 Forced Continuous Conduction Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Small Signal Model
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application Circuit Diagram with Ceramic Output Capacitors
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 External Component Selection
          3. 8.2.1.2.3 External Component Selection Using All Ceramic Output Capacitors
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Application Circuit
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 External Component Selection
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DQP|22
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Over recommended free-air temperature range, VVDD= 12 V (unless otherwise noted)
PARAMETERCONDITIONSMINTYPMAXUNIT
SUPPLY CURRENT
VVINVIN pin power conversion input voltage1.515V
VVDDSupply input voltage4.525V
IVIN(leak)VIN pin leakage currentVEN = 0 V1µA
IVDDVDD supply currentTA = 25°C, No load, VEN = 5 V,
VVFB = 0.630 V		420590µA
IVDDSDNVDD shutdown currentTA = 25°C, No load, VEN = 0 V10µA
INTERNAL REFERENCE VOLTAGE
VVFBVFB regulation voltageCCM condition(1)0.6V
VVFBVFB regulation voltageTA = 25°C0.5970.60.603V
0°C ≤ TA ≤ 85°C0.59520.60.6048
–40°C ≤ TA ≤ 85°C0.5940.60.606
IVFBVFB input currentVVFB = 0.630 V, TA = 25°C0.010.20µA
LDO OUTPUT
VVREGLDO output voltage0 mA ≤ IVREG ≤ 30 mA4.7755.36V
IVREGLDO output current(1)Maximum current allowed from LDO30mA
VDOLow drop out voltageVVDD = 4.5 V, IVREG = 30 mA230mV
BOOT-STRAP SWITCH
VFBSTForward voltageVVREG-VBST, IF = 10 mA, TA = 25°C0.10.2V
IVBSTLKVBST leakage currentVVBST = 23 V, VSW = 17 V, TA = 25°C0.011.50µA
DUTY AND FREQUENCY CONTROL
tOFF(min)Minimum off timeTA = 25°C150260400ns
tON(min)Minimum on timeVIN = 17 V, VOUT = 0.6 V, RRF = 39 kΩ,
TA = 25 °C(1)		35ns
SOFT START
tSSInternal soft-start time from
VOUT = 0 V to 95% of VOUT		RMODE = 39 kΩ0.7ms
RMODE = 100 kΩ1.4
RMODE = 200 kΩ2.8
RMODE = 470 kΩ5.6
INTERNAL MOSFETS
RDS(on)HHigh-side MOSFET on-resistanceTA = 25°C5mΩ
RDS(on)LLow-side MOSFET on-resistanceTA = 25°C2mΩ
POWER GOOD
VTHPGPG thresholdPG in from lower92.5%95.0%98.5%
PG in from higher107.5%110.0%112.5%
PG hysteresis2.5%5.0%7.5%
RPGPG transistor on-resistance153055Ω
tPGDELPG delayDelay for PG in0.811.2ms
LOGIC THRESHOLD AND SETTING CONDITIONS
VENEN VoltageEnable1.8V
Disable0.6
IENEN Input currentVEN = 5 V1.0µA
fSWSwitching frequencyRRF = 0 Ω to GND, TA = 25°C(2)200250300kHz
RRF = 187 kΩ to GND, TA = 25°C(2)250300350
RRF = 619 kΩ, to GND, TA = 25°C(2)350400450
RRF = Open, TA= 25°C(2)450500550
RRF = 866 kΩ to VREG, TA = 25°C(2)580650720
RRF = 309 kΩ to VREG, TA = 25°C(2)670750820
RRF = 124 kΩ to VREG, TA = 25°C(2)770850930
RRF = 0 Ω to VREG, TA = 25°C(2)8809701070
PROTECTION: CURRENT SENSE
ITRIPTRIP source currentVTRIP = 1 V, TA = 25°C9.410.010.6µA
TCITRIPTRIP current temperature coefficientOn the basis of 25°C(1)4700ppm/°C
VTRIPCurrent limit threshold setting rangeVTRIP-GND0.42.4V
VOCLCurrent limit thresholdVTRIP = 2.4 V68.575.081.5mV
VTRIP = 0.4 V7.512.517.5
VOCLNNegative current limit thresholdVTRIP = 2.4 V-315-300-285mV
VTRIP = 0.4 V-58-50-42
VAZCADJAuto zero cross adjustable rangePositive315mV
Negative–15–3
PROTECTION: UVP and OVP
VOVPOVP trip thresholdOVP detect115%120%125%
tOVPDELOVP propagation delayVFB delay with 50-mV overdrive1µs
VUVPOutput UVP trip thresholdUVP detect65%70%75%
tUVPDELOutput UVP propagation delay0.81.01.2ms
tUVPENOutput UVP enable delayFrom enable to UVP workable1.82.63.2ms
UVLO
VUVVREGVREG UVLO thresholdWake up4.004.204.33V
Hysteresis0.25
THERMAL SHUTDOWN
TSDNThermal shutdown thresholdShutdown temperature(1)145°C
Hysteresis(1)10
(1) Ensured by design. Not production tested.
(2) Not production tested. Test condition is VIN= 12 V, VOUT= 1.1 V, IOUT = 10 A using application circuit shown in Figure 8-11.