7.3.1 5-V LDO and VREG Start-Up

The TPS53515 device has an internal 5-V LDO feature using input from VDD and output to VREG. When the VDD voltage rises above 2.8 V, the internal LDO is enabled and outputs voltage to the VREG pin. The VREG voltage provides the bias voltage for the internal analog circuitry. The VREG voltage also provides the supply voltage for the gate drives.

Figure 33. Power-up Sequence Waveforms

7.3.2 Enable, Soft Start, and Mode Selection

The internal LDO regulator starts immediately and regulates to 5 V at the VREG pin.

When the EN pin voltage rises above the enable threshold voltage (typically 1.4 V), the controller enters its start-up sequence. The controller then uses the first 400 μs to calibrate the switching frequency setting resistance attached to the RF pin and stores the switching frequency code in internal registers. During this period, the MODE pin also senses the resistance attached to this pin to determine the operation mode. In the second phase, an internal DAC starts ramping up the reference voltage from 0 V to 0.6 V. the ramping up time is 1 ms. The device maintains smooth and constant ramp-up of the output voltage during start-up regardless of load current.

7.3.3 Frequency Selection

TPS53515 device lets users select the switching frequency by using the RF pin. Table 1 lists the divider ratio and some example resistor values for the switching frequency selection. The 1% tolerance resistors with a typical temperature coefficient of ±100 ppm/ºC are recommended. If the design requires a tighter noise margin for more reliable SW-frequency detection, use higher performance resistors.

space

Equation 1.

where

• R_{RF_L} is the low-side resistance of the RF pin resistor divider
• R_{RF_H} is the high-side resistance of the RF pin resistor divider

7.3.4 D-CAP3 Control and Mode Selection

Figure 34. Internal RAMP Generation Circuit

The TPS53515 device uses D-CAP3 mode control to achieve fast load transient while maintaining the ease-of-use feature. An internal RAMP is generated and fed to the VFB pin to reduce jitter and maintain stability. The amplitude of the ramp is determined by the R-C time-constant as shown in Figure 34. At different switching frequencies, (f_SW) the R-C time-constant varies to maintain relatively constant RAMP amplitude.

7.3.4.1 D-CAP3 Mode

From small-signal loop analysis, a buck converter using the D-CAP3 mode control architecture can be simplified as shown in Figure 35.

Figure 35. D-CAP3 Mode

The D-CAP3 control architecture includes an internal ripple generation network enabling the use of very low-ESR output capacitors such as multilayered ceramic capacitors (MLCC). No external current sensing network or voltage compensators are required with D-CAP3 control architecture. The role of the internal ripple generation network is to emulate the ripple component of the inductor current information and then combine it with the voltage feedback signal to regulate the loop operation. For any control topologies supporting no external compensation design, there is a minimum and/or maximum range of the output filter it can support. The output filter used with the TPS53515 device is a lowpass L-C circuit. This L-C filter has double pole that is described in Equation 2.

Equation 2.

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS53515 device. The low frequency L-C double pole has a 180 degree in phase. At the output filter frequency, the gain rolls off at a –40dB per decade rate and the phase drops rapidly. The internal ripple generation network introduces a high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per decade and increases the phase to 90 degree one decade above the zero frequency.

The inductor and capacitor selected for the output filter must be such that the double pole of Equation 2 is located close enough to the high-frequency zero so that the phase boost provided by the high-frequency zero provides adequate phase margin for the stability requirement.

Table 2. Locating the Zero

SWITCHING FREQUENCIES (fSW) (kHz)	ZERO (fZ) LOCATION (kHz)
250 and 300	6
400 and 500	7
600 and 750	9
850 and 1000	12

After identifying the application requirements, the output inductance should be designed so that the inductor peak-to-peak ripple current is approximately between 25% and 35% of the I_CC(max) (peak current in the application). Use Table 2 to help locate the internal zero based on the selected switching frequency. In general, where reasonable (or smaller) output capacitance is desired, Equation 3 can be used to determine the necessary output capacitance for stable operation.

Equation 3.

If MLCC is used, consider the derating characteristics to determine the final output capacitance for the design. For example, when using an MLCC with specifications of 10-µF, X5R and 6.3 V, the deratings by DC bias and AC bias are 80% and 50%, respectively. The effective derating is the product of these two factors, which in this case is 40% and 4-µF. Consult with capacitor manufacturers for specific characteristics of the capacitors to be used in the system/applications.

Table 3 shows the recommended output filter range for an application design with the following specifications:

• Input voltage, V_IN = 12 V
• Switching frequency, f_SW = 600 kHz
• Output current, I_OUT = 8 A

The minimum output capacitance is verified by the small-signal measurement conducted on the EVM using the following two criteria:

• Loop crossover frequency is less than one-half the switching frequency (300 kHz)
• Phase margin at the loop crossover is greater than 50 degrees

For the maximum output capacitance recommendation, simplify the procedure to adopt an unrealistically high output capacitance for this type of converter design, then verify the small-signal response on the EVM using the following one criteria:

• Phase margin at the loop crossover is greater than 50 degrees

As indicated by the phase margin, the actual maximum output capacitance (C_OUT(max)) can continue to go higher. However, small-signal measurement (bode plot) should be done to confirm the design.

Select a MODE pin configuration as shown in Table 4 to in double the R-C time-constant option for the maximum output capacitance design and application. Select a MODE pin configuration to use single R-C time constant option for the normal (or smaller) output capacitance design and application.

The MODE pin also selects skip-mode or FCCM-mode operation.

Table 3. Recommended Component Values

VOUT (V)	RLOWER (kΩ)	RUPPER (kΩ)	LOUT (µH)	COUT(min) (µF) (1)	CROSS- OVER (kHz)	PHASE MARGIN (°)	COUT(max) (µF) (1)	INTERNAL RC SETTING (µs)	INDUCTOR ΔI/ICC(max)	ICC(max) (A)
0.6	10	0	0.36 PIMB065T-R36MS	3 × 100	247	70		40	33%	8
					48	62	30 x 100	80
1.2		10	0.68 PIMB065T-R68MS	9 × 22	207	53		40	33%
					25	84	30 x 100	80
2.5		31.6	1.2 PIMB065T-1R2MS	4 × 22	185	57		40	34%
					11	63	30 x 100	80
3.3		45.3	1.5 PIMB065T-1R5MS	3 × 22	185	57		40	33%
					9	59	30 x 100	80
5.5		82.5	2.2 PIMB065T-2R2MS	2 × 22	185	51		40	28%
					7	58	30 x 100	80

(1) All C_OUT(min) and C_OUT(max) capacitor specifications are 1206, X5R, 10 V.

For higher output voltage at or above 2.0 V, additional phase boost might be required to secure sufficient phase margin due to phase delay/loss for higher output voltage (large on-time (t_ON)) setting in a fixed on time topology based operation.

A feedforward capacitor placing in parallel with R_UPPER is found to be very effective to boost the phase margin at loop crossover. Refer to TI application note SLVA289 for details.

Table 4. Mode Selection and Internal RAMP R-C Time Constant

MODE SELECTION	ACTION	RMODE (kΩ)	R-C TIME CONSTANT (µs)	SWITCHING FREQUENCIES fSW (kHz)
Skip Mode	Pull down to GND	0	60	250	and	300
			50	400	and	500
			40	600	and	750
			30	850	and	1000
		150	120	250	and	300
			100	400	and	500
			80	600	and	750
			60	850	and	1000
FCCM(1)	Connect to PGOOD	20	60	250	and	300
			50	400	and	500
			40	600	and	750
			30	850	and	1000
		150	120	250	and	300
			100	400	and	500
			80	600	and	750
			60	850	and	1000
FCCM	Connect to VREG	0	120	250	and	300
			100	400	and	500
			80	600	and	750
			60	850	and	1000

(1) Device goes into Forced CCM (FCCM) after PGOOD becomes high.

7.3.4.2 Sample and Hold Circuitry

Figure 36. Sample and Hold Logic Circuitry

The sample and hold circuitry is the difference between D-CAP3 and D-CAP2. The sample and hold circuitry, which is an advance control scheme to boost output voltage accuracy higher on the device, is one of features of the device. The sample and hold circuitry generates a new DC voltage of CSN instead of the voltage which is produced by R_C2 and C_C2 which allows for tight output-voltage accuracy and makes the device more competitive.

Figure 37. Continuous Conduction Mode (CCM) With Sample and Hold Circuitry

Figure 39. Continuous Conduction Mode (CCM) Without Sample and Hold Circuitry

Figure 41. Output Voltage vs Output Current

Figure 38. Discontinuous Conduction Mode (DCM) With Sample and Hold Circuitry

Figure 40. Discontinuous Conduction Mode (DCM) Without Sample and Hold Circuitry

Figure 42. Output Voltage vs Output Current

7.3.5 Power-Good

The TPS53515 device has power-good output that indicates high when switcher output is within the target. The power-good function is activated after the soft-start operation is complete. If the output voltage becomes within ±8% of the target value, internal comparators detect the power-good state and the power-good signal becomes high after a 1-ms internal delay. If the output voltage goes outside of ±16% of the target value, the power-good signal becomes low after a 2-μs internal delay. The power-good output is an open-drain output and must be pulled-up externally.

7.3.6 Current Sense and Overcurrent Protection

The TPS53515 device has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF state and the controller maintains the OFF state during the period that the inductor current is larger than the overcurrent trip level. To provide good accuracy and a cost-effective solution, the TPS53515 device supports temperature compensated MOSFET R_DS(on) sensing. Connect the TRIP pin to GND through the trip-voltage setting resistor, R_TRIP. The TRIP pin sources I_TRIP current, which is 10 μA typically at room temperature, and the trip level is set to the OCL trip voltage V_TRIP as shown in Equation 4.

Equation 4.

where

• V_TRIP is in mV
• R_TRIP is in kΩ
• I_TRIP is in µA

The inductor current is monitored by the voltage between the GND pin and SW pin so that the SW pin is properly connected to the drain pin of the low-side MOSFET. I_TRIP has a 3000-ppm/°C temperature slope to compensate the temperature dependency of R_DS(on). The GND pin acts as the positive current-sensing node. Connect the GND pin to the proper current sensing device, (for example, the source pin of the low-side MOSFET.)

Because the comparison occurs during the OFF state, V_TRIP sets the valley level of the inductor current. Thus, the load current at the overcurrent threshold, I_OCP, is calculated as shown in Equation 5.

Equation 5.

where

• R_DS(on)L is the on-resistance of the low-side MOSFET
• R_TRIP is in kΩ

Equation 5 calculates the typical DC OCP level (typical low-side on-resistance [R_DS(on)] of 5.9 mΩ should be used); to design for worst case minimum OCP, maximum low-side on-resistance value of 8 mΩ should be used.

During an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output voltage tends to decrease. Eventually, the output voltage crosses the undervoltage-protection threshold and shuts down.

For the TPS53515 device, the overcurrent protection maximum is recommended up to 14 A only.

7.3.7 Overvoltage and Undervoltage Protection

The TPS53515 device monitors a resistor-divided feedback voltage to detect overvoltage and undervoltage. When the feedback voltage becomes lower than 68% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins counting. After 1 ms, the TPS53515 device latches OFF both high-side and low-side MOSFETs drivers. The UVP function enables after soft-start is complete.

When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes high and the circuit latches OFF the high-side MOSFET driver and turns on the low-side MOSFET until reaching a negative current limit. Upon reaching the negative current limit, the low-side FET is turned off and the high-side FET is turned on again for a minimum on-time. The TPS53515 device operates in this cycle until the output voltage is pulled down under the UVP threshold voltage for 1 ms. After the 1-ms UVP delay time, the high-side FET is latched off and low-side FET is latched on. The fault is cleared with a reset of VDD or by retoggling the EN pin.

7.3.8 Out-of-Bounds Operation

The device has an out-of-bounds (OOB) overvoltage protection that protects the output load at a much lower overvoltage threshold of 8% above the target voltage. OOB protection does not trigger an overvoltage fault, so the device is not latched off after an OOB event. OOB protection operates as an early no-fault overvoltage-protection mechanism. During the OOB operation, the controller operates in forced PWM mode only by turning on the low-side FET. Turning on the low-side FET beyond the zero inductor current quickly discharges the output capacitor thus causing the output voltage to fall quickly toward the setpoint. During the operation, the cycle-by-cycle negative current limit is also activated to ensure the safe operation of the internal FETs.

7.3.9 UVLO Protection

The TPS53515 device monitors the voltage on the VDD pin. If the VDD pin voltage is lower than the UVLO off-threshold voltage, the switch mode power supply shuts off. If the VDD voltage increases beyond the UVLO on-threshold voltage, the controller turns back on. UVLO is a nonlatch protection.

7.3.10 Thermal Shutdown

The TPS53515 device monitors internal temperature. If the temperature exceeds the threshold value (typically 140°C), TPS53515 device shuts off. When the temperature falls approximately 40°C below the threshold value, the device turns on. Thermal shutdown is a nonlatch protection.

7.4.1 Auto-Skip Eco-mode Light Load Operation

While the MODE pin is pulled to GND directly or through 150-kΩ resistor, the TPS53515 device automatically reduces the switching frequency at light-load conditions to maintain high efficiency. This section describes the operation in detail.

As the output current decreases from heavy load condition, the inductor current also decreases until the rippled valley of the inductor current touches zero level. Zero level is the boundary between the continuous-conduction and discontinuous-conduction modes. The synchronous MOSFET turns off when this zero inductor current is detected. As the load current decreases further, the converter runs into discontinuous-conduction mode (DCM). The on-time is maintained to a level approximately the same as during continuous-conduction mode operation so that discharging the output capacitor with a smaller load current to the level of the reference voltage requires more time. The transition point to the light-load operation I_O(LL) (for example: the threshold between continuous- and discontinuous-conduction mode) is calculated as shown in Equation 6.

Equation 6.

where

• f_SW is the PWM switching frequency

Using only ceramic capacitors is recommended for Auto-skip mode.

7.4.2 Forced Continuous-Conduction Mode

When the MODE pin is tied to the PGOOD pin through a resistor, the controller operates in continuous conduction mode (CCM) during light-load conditions. During CCM, the switching frequency maintained to an almost constant level over the entire load range which is suitable for applications requiring tight control of the switching frequency at the cost of lower efficiency.