SLUSCJ3A April   2016  – June 2016 TPS53632G

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  7. 7 Timing Requirements
  8. 8 Switching Characteristics
  9. 9 Typical Characteristics (Half-Bridge Operation)
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Current Sensing
      2. 10.3.2  Load Transients
      3. 10.3.3  PWM and SKIP Signals
      4. 10.3.4  5-V, 3.3-V and 1.8-V Undervoltage Lockout (UVLO)
      5. 10.3.5  Output Undervoltage Protection (UVP)
      6. 10.3.6  Overcurrent Protection (OCP)
      7. 10.3.7  Overvoltage Protection
      8. 10.3.8  Analog Current Monitor, IMON and Corresponding Digital Output Current
      9. 10.3.9  Addressing
      10. 10.3.10 I2C Interface Operation
        1. 10.3.10.1 Key for Protocol Examples
        2. 10.3.10.2 Protocol Examples
      11. 10.3.11 Start-Up Sequence
      12. 10.3.12 Power Good Operation
      13. 10.3.13 Fault Behavior
    4. 10.4 Device Functional Modes
      1. 10.4.1 PWM Operation
    5. 10.5 Configuration and Programming
      1. 10.5.1 Operating Frequency
      2. 10.5.2 Overcurrent Protection (OCP) Level
      3. 10.5.3 IMON Gain
      4. 10.5.4 Slew Rate
      5. 10.5.5 Base Address
      6. 10.5.6 Ramp Selection
      7. 10.5.7 Active Phases
    6. 10.6 Register Maps
      1. 10.6.1 Voltage Select Register (VSR) (00h)
      2. 10.6.2 IMON Register (03h)
      3. 10.6.3 VMAX Register (04h)
      4. 10.6.4 Power State Register (06h)
      5. 10.6.5 SLEW Register (07h)
      6. 10.6.6 Lot Code Registers (10-13h)
      7. 10.6.7 Fault Register (14h)
  11. 11Applications and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 D-CAP+™ Half-Bridge Application
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Detailed Design Procedure
          1. 11.2.1.2.1 Step 1: Select Switching Frequency
          2. 11.2.1.2.2 Step 2: Set The Slew Rate
          3. 11.2.1.2.3 Step 3: Determine Inductor Value And Choose Inductor
          4. 11.2.1.2.4 Step 4: Determine Current Sensing Method
          5. 11.2.1.2.5 Step 5: DCR Current Sensing
          6. 11.2.1.2.6 Step 6: Select OCP Level
          7. 11.2.1.2.7 Step 7: Set the Load-Line Slope
          8. 11.2.1.2.8 Step 8: Current Monitor (IMON) Setting
        3. 11.2.1.3 Application Performance Plots
        4. 11.2.1.4 Loop Compensation for Zero Load-Line
  12. 12Power Supply Recommendations
  13. 13 Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 PCB Layout
      2. 13.1.2 Current Sensing Lines
      3. 13.1.3 Feedback Voltage Sensing Lines
      4. 13.1.4 PWM And SKIP Lines
        1. 13.1.4.1 Minimize High Current Loops
      5. 13.1.5 Power Chain Symmetry
      6. 13.1.6 Component Location
      7. 13.1.7 Grounding Recommendations
      8. 13.1.8 Decoupling Recommendations
      9. 13.1.9 Conductor Widths
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Trademarks
    2. 14.2 Electrostatic Discharge Caution
    3. 14.3 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RSM Package
32-Pin QFN
Top View
TPS53632G pinout_rsm32_slusbw8.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
COMP 26 I Error amplifier summing node. Resistors between the VREF pin and the COMP pin (RCOMP) and between the COMP pin and the DROOP pin (RDROOP) set the droop gain.
CSP1 17 I Positive current sense inputs. Connect to the most positive node of current sense resistor or inductor DCR sense network. Tie CSP2 or CSP1 (in that order) to a 3.3-V supply to disable the phase.
CSP2 20
PU3 21 Connect to 3.3-V supply.
CSN1 18 I Negative current sense inputs. Connect to the most negative node of current sense resistor or inductor DCR sense network. CSN1 has a secondary OVP comparator and includes the soft-stop, pull-down transistor.
CSN2 19
NC 22 – No connect.
DROOP 25 O Error amplifier output. A resistor pair between this pin and the VREF pin and between the COMP pin and this pin sets the droop gain. ADROOP = 1 + RDROOP / RCOMP.
EN 8 I Enable. 100-ns de-bounce. Regulator enters low-power mode, but retains start-up settings when brought low.
FREQ-P 10 I A resistor between this pin and GND sets the per-phase switching frequency. Add a resistor to VREF to disable dynamic phase add and drop operation.
GFB 23 I Voltage sense return. Tie to GND on PCB with a 10-Ω resistor to provide feedback when the microprocessor is not populated.
GND 29 – Analog circuit reference. Tie this pin to a quiet point on the ground plane.
IMON 13 O Analog current monitor output. VIMON = ΣVISENSE × (1 + RIMON/ROCP).
OCP-I 12 I/O Voltage divider to IMON. Resistor ratio sets the IMON gain (see IMON pin). A resistor between this pin and GND (ROCP) selects 1 of 8 OCP levels (per phase, latched at start-up).
PU 9 I Pull-up to VREF through 10-kΩ resistor.
PGOOD 3 O Power good output. Open-drain.
PWM-HI 6 O PWM controls for the external driver; 5-V logic level. Controller forces signal to the tri-state level when needed.
PWM-LO 5
NC 4 – No connect.
NC 30 – No connect.
32
RAMP 11 I Voltage divider to VREF. A resistor to GND sets the ramp setting voltage. The RAMP setting can be used to override the factory ramp setting.
SCL 31 I Serial digital clock line.
SDA 1 I/O Serial digital I/O line.
SKIP 7 O When high, the driver enters FCCM mode; otherwise, the driver is in DCM mode. Driving the tri-state level on this pin puts the drivers into a low power sleep mode.
SLEWA 15 I The voltage sets the 3 LSBs of the I2C address. The resistance to GND selects 1 of 8 slew rates. The start-up slew rate (EN transitions high) is SLEWRATE/2. The ADDRESS and SLEWRATE values are latched at start-up.
VINTF 14 I Input voltage to interface logic. Voltage level can be between 1.62 V and 3.5 V.
V5A 28 I 5-V power input for analog circuits; connect through resistor to 5-V plane and bypass to GND with ceramic capacitor with a value of at least 1 µF.
VBUS 16 I The VBUS pin provides input voltage information to the on-time circuits for both converters.
VDD 2 I 3.3-V digital power input. Bypass this pin to GND with a capacitor with a value of at least 1 µF.
VFB 24 I Voltage sense line. Tie directly to VOUT sense point of processor. Tie to VOUT on PCB with a 10-Ω resistor to provide feedback when the microprocessor is not populated. The resistance between VFB and GFB is > 1 MΩ
VREF 27 O 1.7-V, 500-µA reference. Bypass to GND with a 0.22-µF ceramic capacitor.
PAD GND – Thermal pad Tie to the ground plane with multiple vias.