SLUSC40B July   2016  – February 2017 TPS53667

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I/O Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  V3R3 LDO
      2. 7.3.2  PWM Operation
      3. 7.3.3  Current Sense and IMON Calculation
      4. 7.3.4  Setting the Load-Line (DROOP)
      5. 7.3.5  Load Transitions
      6. 7.3.6  Overshoot Reduction (OSR)
      7. 7.3.7  Undershoot Reduction (USR)
      8. 7.3.8  AutoBalance™ Current Sharing
      9. 7.3.9  Phase Overlap
      10. 7.3.10 VID
      11. 7.3.11 PWM and SKIP Signals
      12. 7.3.12 TSEN (Thermal Sense) Pin
      13. 7.3.13 RESET Function
      14. 7.3.14 Input UVLO
      15. 7.3.15 V5 Pin Undervoltage Lockout (UVLO)
      16. 7.3.16 Output Undervoltage Protection (UVP)
      17. 7.3.17 Overvoltage Protection (OVP)
      18. 7.3.18 Overcurrent Limit (OCL) and Overcurrent Protection (OCP)
      19. 7.3.19 Current Sharing Warning and Phase Fault Detect
      20. 7.3.20 Turn off Individual Phase by PMBus
      21. 7.3.21 Phase Shedding
      22. 7.3.22 Over Temperature Protection (OTP)
      23. 7.3.23 VR_HOT and VR_FAULT Indication
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 User Selections
        1. 7.5.1.1  Switching Frequency
        2. 7.5.1.2  IMAX Information
        3. 7.5.1.3  Boot Voltage
        4. 7.5.1.4  Per-Phase Overcurrent Limit (OCL) Level
        5. 7.5.1.5  Overshoot Reduction (OSR) and Undershoot Reduction (USR) Levels
        6. 7.5.1.6  Slew Rate Selection
        7. 7.5.1.7  Mode Selections
        8. 7.5.1.8  Soft Start Slew Rate and PMBus Addresses
        9. 7.5.1.9  Ramp Selection
        10. 7.5.1.10 Maximum Active Phase Numbers
        11. 7.5.1.11 Pinstrap Mode Settings
        12. 7.5.1.12 NVM Default Settings
        13. 7.5.1.13 6-Phase Application
        14. 7.5.1.14 6-Phase NVM Application
      2. 7.5.2 Supported Protections and Fault Reports
      3. 7.5.3 Supported PMBus Address and Commands Summary
        1. 7.5.3.1 Address Selection
        2. 7.5.3.2 Commands Summary
    6. 7.6 Register Maps
      1. 7.6.1 PMBus Description
        1. 7.6.1.1 PMBus General
        2. 7.6.1.2 PMBus Connections
        3. 7.6.1.3 Supported Data Formats
        4. 7.6.1.4 PMBus Command Format
      2. 7.6.2 PMBus Functionality
        1. 7.6.2.1 PMBus Address
        2. 7.6.2.2 Pin Strap Settings
        3. 7.6.2.3 Supported PMBus Commands
          1. 7.6.2.3.1  OPERATION (01h)
          2. 7.6.2.3.2  ON_OFF_CONFIG (02h)
          3. 7.6.2.3.3  CLEAR_FAULTS (03h)
          4. 7.6.2.3.4  WRITE_PROTECT (10h)
          5. 7.6.2.3.5  STORE_DEFAULT_ALL (11h)
          6. 7.6.2.3.6  RESTORE_DEFAULT_ALL (12h)
          7. 7.6.2.3.7  CAPABILITY (19h)
          8. 7.6.2.3.8  VOUT_MODE (20h)
          9. 7.6.2.3.9  VOUT_COMMAND (21h)
          10. 7.6.2.3.10 VOUT_MAX (24h)
          11. 7.6.2.3.11 VOUT_MARGIN_HIGH (25h)
          12. 7.6.2.3.12 VOUT_MARGIN_LOW (26h)
          13. 7.6.2.3.13 IOUT_CAL_OFFSET (39h)
          14. 7.6.2.3.14 VOUT_OV_FAULT_RESPONSE (41h)
          15. 7.6.2.3.15 VOUT_UV_FAULT_RESPONSE (45h)
          16. 7.6.2.3.16 IOUT_OC_FAULT_LIMIT (46h)
          17. 7.6.2.3.17 IOUT_OC_FAULT_RESPONSE (47h)
          18. 7.6.2.3.18 IOUT_OC_WARN_LIMIT (4Ah)
          19. 7.6.2.3.19 OT_FAULT_LIMIT (4Fh)
          20. 7.6.2.3.20 OT_FAULT_RESPONSE (50h)
          21. 7.6.2.3.21 OT_WARN_LIMIT (51h)
          22. 7.6.2.3.22 VIN_OV_FAULT_LIMIT (55h)
          23. 7.6.2.3.23 IIN_OC_FAULT_LIMIT (5Bh)
          24. 7.6.2.3.24 IIN_OC_FAULT_RESPONSE (5Ch)
          25. 7.6.2.3.25 IIN_OC_WARN_LIMIT (5Dh)
          26. 7.6.2.3.26 STATUS_BYTE (78h)
          27. 7.6.2.3.27 STATUS_WORD (79h)
          28. 7.6.2.3.28 STATUS_VOUT (7Ah)
          29. 7.6.2.3.29 STATUS_IOUT (7Bh)
          30. 7.6.2.3.30 STATUS_INPUT (7Ch)
          31. 7.6.2.3.31 STATUS_TEMPERATURE (7Dh)
          32. 7.6.2.3.32 STATUS_CML (7Eh)
          33. 7.6.2.3.33 STATUS_MFR_SPECIFIC (80h)
          34. 7.6.2.3.34 READ_VIN (88h)
          35. 7.6.2.3.35 READ_IIN (89h)
          36. 7.6.2.3.36 READ_VOUT (8Bh)
          37. 7.6.2.3.37 READ_IOUT (8Ch)
          38. 7.6.2.3.38 READ_TEMPERATURE_1 (8Dh)
          39. 7.6.2.3.39 READ_POUT (96h)
          40. 7.6.2.3.40 READ_PIN (97h)
          41. 7.6.2.3.41 PMBus_REVISION (98h)
          42. 7.6.2.3.42 MFR_ID (99h)
          43. 7.6.2.3.43 MFR_MODEL (9Ah)
          44. 7.6.2.3.44 MFR_REVISION (9Bh)
          45. 7.6.2.3.45 MFR_DATE (9Dh)
          46. 7.6.2.3.46 MFR_VOUT_MIN (A4h)
          47. 7.6.2.3.47 MFR_SPECIFIC_00 (Per-Phase Overcurrent Limit) (D0h)
          48. 7.6.2.3.48 MFR_SPECIFIC_01 (Telemetry Averaging Time) (D1h)
          49. 7.6.2.3.49 MFR_SPECIFIC_04 (Read VOUT) (D4h)
          50. 7.6.2.3.50 MFR_SPECIFIC_05 (VOUT Trim) (D5h)
          51. 7.6.2.3.51 MFR_SPECIFIC_07 (Additional Function Bits) (D7h)
          52. 7.6.2.3.52 MFR_SPECIFIC_08 (Droop) (D8h)
          53. 7.6.2.3.53 MFR_SPECIFIC_09 (OSR/USR) (D9h)
          54. 7.6.2.3.54 MFR_SPECIFIC_10 (Maximum Operating Current) (DAh)
          55. 7.6.2.3.55 MFR_SPECIFIC_11 (VBOOT) (DBh)
          56. 7.6.2.3.56 MFR_SPECIFIC_12 (Switching Frequency and TRISE) (DCh)
          57. 7.6.2.3.57 MFR_SPECIFIC_13 (Slew Rate and Other Operation Modes) (DDh)
          58. 7.6.2.3.58 MFR_SPECIFIC_14 (Ramp Height) (DEh)
          59. 7.6.2.3.59 MFR_SPECIFIC_15 (Dynamic Phase Shedding Thresholds) (DFh)
          60. 7.6.2.3.60 MFR_SPECIFIC_16 (VIN UVLO) (E0h)
          61. 7.6.2.3.61 MFR_SPECIFIC_19 (E3h)
          62. 7.6.2.3.62 MFR_SPECIFIC_20 (Maximum Operational Phase Number) (E4h)
          63. 7.6.2.3.63 MFR_SPECIFIC_21 (VIN UVLO) (E5h)
          64. 7.6.2.3.64 MFR_SPECIFIC_22 ( VOUT_UV_FAULT_threshold) (E6h)
          65. 7.6.2.3.65 MFR_SPECIFIC_23 (E7h)
          66. 7.6.2.3.66 MFR_SPECIFIC_24 (E8h)
          67. 7.6.2.3.67 MFR_SPECIFIC_44 (DEVICE_CODE) (FCh)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Select the Switching Frequency
        2. 8.2.2.2  Set the Maximum Output Current (IMAX)
        3. 8.2.2.3  Select the Soft-Start Slew Rate
        4. 8.2.2.4  Select the Operation Mode
        5. 8.2.2.5  Choose Inductor
        6. 8.2.2.6  Select the Per-Phase Valley Current Limit And Ramp Level
        7. 8.2.2.7  Set the Load-Line
        8. 8.2.2.8  Set the BOOT Voltage
        9. 8.2.2.9  Set OSR/USR Thresholds to Improve Load Transient Performance
        10. 8.2.2.10 Digital Current Monitor (IMON) Gain and Filter Setting
        11. 8.2.2.11 Compensation Design
        12. 8.2.2.12 Set PMBus Addresses
        13. 8.2.2.13 Programming the Device with the PMBus
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Schematic Review Checklist
      2. 10.1.2 PCB Design Guidelines
        1. 10.1.2.1 Layer Stack-up, 8-Layer PCB as example
        2. 10.1.2.2 Current Sensing Lines
        3. 10.1.2.3 Feedback Voltage Sensing Lines
        4. 10.1.2.4 PWM Lines
        5. 10.1.2.5 Power Chain Symmetry
        6. 10.1.2.6 Placing Analog Signal Components
        7. 10.1.2.7 Grounding Recommendations
        8. 10.1.2.8 TI Smart Power Stage CSD95490Q5MC
          1. 10.1.2.8.1 Electrical Performance
          2. 10.1.2.8.2 Thermal Performance
          3. 10.1.2.8.3 Sensing Performance
        9. 10.1.2.9 Power Delivery and Power Density
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 8-bit Selectable BOOT Voltage via Pinstrap or NVM: 0.5 V to 2.5 V (down to 5-mV Step)
  • 1-, 2-, 3-, 4-, 5-, or 6- Phase Operation
  • PMBus™ System Interface for Telemetry of Voltage, Current, Power, Temperature, and Fault Conditions
  • 1.8-V and 3.3-V PMBus Bias Compatible
  • Fault Reporting: Output Voltage, Output Current, and Temperature
  • Configurable with Non-Volatile Memory (NVM) or Resistor Pinstrap
  • 16 Levels of Programmable Per-Phase OCL with Pinstrap or NVM
  • Fast Transient with DCAP+™Control
  • Optimized Efficiency at Light and Heavy Loads
  • Support Pre-Bias Startup
  • Phase Current Imbalance Detection and Reporting
  • 8 Independent Levels of Overshoot Reduction (OSR) and Undershoot Reduction (USR)
  • Driverless Configuration for Efficient High-Frequency Switching
  • Compatible with CSD9549x NexFET™ Power Stages
  • Accurate, Adjustable Voltage Positioning
  • 300-kHz to 1-MHz Frequency Selections with Closed-loop Frequency Control
  • Patented AutoBalance™ Phase Balancing
  • Uses TI’s Fusion Digital Power Designer GUI
  • Dynamic Phase Shedding with Programmable Current Threshold
  • Conversion Voltage Range: 4.5 V to 17 V
  • Small, 6 mm × 6 mm, 40-Pin, QFN, PowerPAD™ Package

2 Applications

  • Application-Specific Integrated Circuit (ASIC) Power in Communications Equipment
  • High Density Power Solutions
  • Server Power
  • Smart Power Systems

3 Description

The TPS53667 is a high-current, multi-phase, step-down controller. The device offers built-in non volatile memory (NVM) and PMBus interface. It is compatible with the NexFET power stages (CSD9549x). The TPS53667 provides 8-bit BOOT voltage selection covering output voltage from 0.5 V to 2.5 V, with steps as small as 5 mV, which is ideal for high current application with accurate output voltage setting. Advanced control features such as D-CAP+ architecture with undershoot reduction (USR) and overshoot reduction (OSR) provide fast transient response, lowest output capacitance, and high efficiency. The TPS53667 also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at light loads. In addition, the TPS53667 supports the PMBus communication interface with systems for telemetry of voltage, current, power, temperature, and fault conditions. Some of the configurations can be programmed by pinstrap or PMBus and stored in non-volatile memory to minimize the external component count.

The TPS53667 is offered in a space saving, thermally enhanced 40-pin QFN package and is rated to operate from –40°C to 125°C.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPS53667 QFN (40) 6.00 mm × 6.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

TPS53667 fp_simp_app_tps53667_slusc40.gif