SLUSDP0 Data sheet

SLUSDP0A August 2019 – May 2021 TPS53676

PRODUCTION DATA

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7.6.4 On-time control: adaptive t_on and autobalance current sharing

The nominal on-time for each phase is determined by an adaptive one-shot circuit, which generates on-times according to Equation 34. PWM on-times are adjusted very slowly compared to off-times, so the DCAP+ modulator behaves similar to a constant-on-time architecture.

Use the FREQUENCY_SWITCH command to set the nominal per-phase switching frequency.

Equation 34.

t_{ON} = \frac{V_{DAC} + K_{ISHARE} \times (I_{L} - I_{AVG})}{V_{IN} \times FREQUENCY_SWITCH} + ΔPLL_CLF

where

t_ON is the on-time for the phase in seconds
V_DAC is the output voltage set-point in volts
FREQUENCY_SWITCH is the commanded switching frequency in Hz
V_IN is the sensed input voltage from the VIN_CSNIN pin
K_ISHARE is the gain of the current share loop
I_L is the current carried by the phase
I_AVG is the average phase current for all phases
ΔPLL_CLF is the on-time adjustment from the closed loop frequency correction circuit

Current sharing is implemented by adapting the on-time for each phase, according to the difference between its own phase current I_L, and the average of all phase currents I_AVG. When the phase current for any one phase is greater than the average of all phase currents, the on-time of that phase is reduced accordingly. Similarly, if the phase current of any one phase is less than the average of all phase currents, the on-time of that phase is increased.

The on-time is also proportional to the sensed input voltage, which provides the controller with inherent input voltage feed-forward.

Furthermore, a frequency control loop adjusts the on-times for each phase to drive the actual switching frequency equal to the FREQUENCY_SWITCH setting. An internal clock counts the number of observed pulses over a set interval, and compares the result to the calculated ideal number. If too many pulses are fired in the sampling period, the switching frequency is too high, and the on-times are increased to reduce the steady-state switching frequency. If too few pulses are fired during the sampling period, the switching frequency is too low and the on-times are reduced to increase the steady-state frequency. The PWM pin assigned to ORDER=0 is used for counting purposes, as it does not drop due to phase shedding.

Figure 7-22 On-time generation and auto-balance current sharing

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7.6.4 On-time control: adaptive ton and autobalance current sharing

7.6.4 On-time control: adaptive t_on and autobalance current sharing