5 Pin Configuration and Functions

Figure 5-1 RSL Package 48-Pin QFN (Top View)

Table 5-1 Default Functionality of Multifunction Pins

PIN⁽¹⁾	DEFAULT
7, 8, 31, 32	APWM, ACSP
6, 33	BPWM, BCSP
19	BVR_EN
43	BTSEN
44	ATSEN

(1) Default settings can be changed through NVM settings

Table 5-2 Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
ACSP1	27	I	Current sense input for channel A. Connect to the IOUT pin of TI smart power stages. Float unused CSP pins.
ACSP2	28	I
ACSP3	29	I
ACSP4	30	I
ACSP5 / BCSP3	31	I	Current sense input for phase 7 of channel A or phase 3 of channel B. Float unused CSP pins.
ACSP6 / BCSP2	32	I	Current sense input for phase 7 of channel A or phase 2 of channel B. Float unused CSP pins.
ACSP7 / BCSP1	33	I	Current sense input for phase 7 of channel A or phase 1 of channel B. Float unused CSP pins.
NC	34	-	Do not connect.
NC	35	-	Do not connect.
NC	36	-	Do not connect.
NC	37	-	Do not connect.
NC	38	-	Do not connect.
ADDR	42	I	Voltage divider to VREF and GND. The value of a resistor connected between this pin and GND and the voltage level set the PMBus address. Latched at VCC power up. Use the PIN_DETECT_OVERRIDE command to select addresses which are not available through pinstrap.
APWM1	12	O	PWM signal for phase 1 of channel A. Float unused PWM pins.
APWM2	11	O	PWM signal for phase 2 of channel A. Float unused PWM pins.
APWM3	10	O	PWM signal for phase 3 of channel A. Float unused PWM pins.
APWM4	9	O	PWM signal for phase 4 of channel A. Float unused PWM pins.
APWM5 / BPWM3	8	O	PWM signal for phase 5 of channel A, or phase 3 of channel B. Float unused PWM pins.
APWM6 / BPWM2	7	O	PWM signal for phase 6 of channel A, or phase 2 of channel B. Float unused PWM pins.
APWM7 / BPWM1	6	O	PWM signal for phase 7 of channel A, or phase 1 of channel B. Float unused PWM pins.
NC	5	-	Do not connect.
NC	4	-	Do not connect.
NC	3	-	Do not connect.
NC	2	-	Do not connect.
NC	1	-	Do not connect.
ATSEN / BTSEN	44	I	Multi-function pin. Configure through PMBus. ATSEN (default): Connect to the TAO pin of the TI smart power stages of channel A to sense the highest temperature of the power stages and to sense the built-in fault signal from the power stages. BTSEN: Connect to the TAO pin of the TI smart power stages of channel B to sense the highest temperature of the power stages and to sense the built-in fault signal from the power stages. Float unused TSEN pins.
AVR_EN	17	I	Active high enable input for channel A. By default, asserting the AVR_EN pin activates channel A. Polarity and enable conditions are programmable through ON_OFF_CONFIG.
AVR_RDY	16	O	VRD "Ready" output signal of channel A. This open drain output requires an external pull-up resistor. The AVR_RDY pin is pulled low when a shutdown fault occurs.
AVSN	26	I	Negative input of the remote voltage sense of channel A.
AVSP	25	I	Positive input of the remote voltage sense of channel A.
AVS_CLK	21	I	AVSBus clock input.
AVS_MDATA	22	I	AVSBus master data (MOSI)
AVS_SDATA	23	O	AVSBus slave data (MISO)
AVS_VDDIO	24	I	AVSBus supply pin. Bypass to ground with minimum 1uF effective ceramic capacitance and connect to a well regulated supply voltage which supplies the logic levels for the AVS communication interface.
BOOT_CHA	18	I	Pinstraps for Channel A boot voltage (8 bits). Use the PIN_DETECT_OVERRIDE command to select options which are not available through pinstrap.
BTSEN / ATSEN / TSEN	43	I	Multi-function pin. Configure through PMBus. BTSEN (default): Connect to the TAO pin of the TI smart power stages of channel B to sense the highest temperature of the power stages and to sense the built-in fault signal from the power stages. BTSEN: Connect to the TAO pin of the TI smart power stages of channel A to sense the highest temperature of the power stages and to sense the built-in fault signal from the power stages. TSEN: Connect to the TAO pin of the TI smart power stages of channels A and B to sense the highest temperature of the power stages and to sense the built-in fault signal from the power stages. Float unused TSEN pins.
BVR_EN / RESET# / SYNC	19	I/O	Multi-function pin. Configure through PMBus. BVR_EN (Default) : Active high enable input for channel B. Asserting the BVR_EN pin activates channel B. Polarity and enable conditions are programmable through ON_OFF_CONFIG. RESET#: Active low signal which causes both channels output voltage target to revert to their respective VBOOT values when asserted. Pull-up to 3.3 V. SYNC: If assigned as an output, this pin provides a free-running clock for other TPS53676 devices to synchronize to. If assigned as an input, an internal phase locked-loop can synchronize switching of one or both channels to a clock supplied to this pin. Phase shift and data direction are programmable through NVM.
BVR_RDY	20	O	VRD "Ready" output signal of channel B. This open drain output requires an external pull-up resistor. The BVR_RDY pin is pulled low when a shutdown fault occurs.
BVSN	39	I	Negative input of the remote voltage sense of channel B. If channel B is not used, connect BVSN to GND.
BVSP	40	I	Positive input of the remote voltage sense of channel B. If channel B is not used, connect BVSP to GND.
CSPIN	45	I	Positive terminal of the integrated high-side current sensing amplifier. Connect to the supply side of the input current sense element. Tie to VIN_CSNIN, and to the input voltage, if measured input current sensing is not used.
SMB_ALERT#	15	O	SMBus or I²C bi-directional alert pin interface. (Open drain)
SMB_CLK	14	I	SMBus or I²C serial clock interface. (Open drain)
SMB_DIO	13	I/O	SMBus or I²C bi-directional serial data interface. (Open drain)
VCC	47	P	3.3-V power input. Bypass to GND with a ceramic capacitor with a value greater than or equal to 1 µF. Used to power all digital logic circuits.
VIN_CSNIN	46	I	Negative terminal of the integrated high-side current sense amplifier. Connect to the power-stage side of the current sense element. The VIN_CSNIN voltage is also used to determine the correct on-time for the converter. Tie to CSPIN, and to the input voltage, if measured input current sensing is not used.
VREF	48	O	1.5-V LDO reference voltage. Bypass to GND with 1-µF effective ceramic capacitor. Connect the VREF pin to the REFIN pin of the TI smart power stages as the current sense common-mode voltage.
VR_FAULT#	41	O	VR fault indicator. (Open-drain). The failures include the high-side FETs short, over-voltage, over-temperature, and the input over-current conditions. Use the fault signal on the platform to remove the power source by turning off the AC power supply. When the failure occurs, the VR_FAULT# pin is LOW, and put the controller into latch-off mode.
Thermal Pad		G	Analog ground pad. Connect to GND plan with vias.

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Mechanical Data (Package|Pins)

Thermal pad, mechanical data (Package|Pins)

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5 Pin Configuration and Functions