SLUSFE9
September 2023
TPS53689T
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Revision History
5
Device and Documentation Support
5.1
Documentation Support
5.2
Receiving Notification of Documentation Updates
5.3
Support Resources
5.4
Trademarks
5.5
Electrostatic Discharge Caution
5.6
Glossary
6
Mechanical, Packaging, and Orderable Information
6.1
Package Option Addendum
6.2
Packaging Information
6.3
Tape and Reel Information
7
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RSB|40
MPQF185C
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slusfe9_oa
1
Features
Input voltage range: 4.5 V to 17 V
Output voltage range: 0.25 V to 5.5 V
Dual output supporting N+M phase configurations (N+M ≤
8
, M ≤
4
)
Native trans-inductor voltage regulator (TLVR) topology support, with L
C
open and short protection
Fully compatible with TI smart power stages
Supports voltage- and current-source Imon power stages, with internal 1 kΩ resistor
Support for traditional (legacy mode) and limp mode power stage fault identification
Supports dual side power delivery with 12"+ trace length
Intel®
VR14 SVID compliant with PSYS support
Backward compatible to VR13.HC/VR13.0 SVID
Automatic NVM fault status logging
Enhanced D-CAP+ control to provider superior transient performance with excellent dynamic current sharing
Dynamic phase shedding with programmable thresholds for optimizing efficiency at light and heavy loads
Configurable with non-volatile memory (NVM) for low external component count
Individual per-phase IMON calibration, with multi-slope gain calibration to increase system accuracy
Diode braking with programmable timeout for reduced transient overshoot
Programmable per-phase valley current limit (OCL)
PMBus™
v1.3.1 system interface for telemetry of voltage, current, power, temperature, and fault conditions
Programmable loop compensation through PMBus
5.00 mm × 5.00mm
,
40
-pin, QFN package