SLUSB56B November 2012 – April 2019 TPS53819A
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY CURRENT | ||||||
IVDD | VDD bias current | TA = 25°C, no load, power conversion enabled (no switching) | 920 | μA | ||
IVDDSTBY | VDD standby current | TA = 25°C, no load, power conversion disabled | 610 | μA | ||
INTERNAL REFERENCE AND FEEDBACK REGULATION VOLTAGE | ||||||
VFB | Feedback regulation voltage | FB w/r/t GND, CCM condition | 600 | mV | ||
VFBTOL | Feedback voltage tolerance | FB w/r/t GND, 0°C ≤ TJ ≤ 85°C | 597 | 600 | 603 | mV |
VDACTOL1 | DAC voltage tolerance 1 | FB w/r/t GND, 0°C ≤ TA ≤ 85°C, all settings with VOUT_ADJUSTMENT only | –4.8 | 4.8 | mV | |
VDACTOL2 | DAC voltage tolerance 2 | FB w/r/t GND, 0°C ≤ TA ≤ 85°C, all settings with VOUT_MARGIN only | –4.8 | 4.8 | mV | |
VDACTOL3 | DAC voltage tolerance 3 | FB w/r/t GND, 0°C ≤ TA ≤ 85°C, with VOUT_ADJUSTMENT = 0Dh and VOUT_MARGIN = 70h for +5% | –4.8 | 4.8 | mV | |
VDACTOL4 | DAC voltage tolerance 4 | FB w/r/t GND, 0°C ≤ TA ≤ 85°C, with VOUT_ADJUSTMENT = 13h and VOUT_MARGIN = 07h for -5% | –4.8 | 4.8 | mV | |
VIOS_LPCMP | Loop comparator input offset voltage | VREF to VFB, TA = 25°C | –2.5 | 2.5 | mV | |
IFB | FB pin input current | VFB = 600 mV | –1 | 1 | μA | |
OUTPUT VOLTAGE | ||||||
IVODIS | VO discharge current | VVO = 0.5 V, power conversion disabled | 10 | 12 | mA | |
DRIVER | ||||||
RDRVH | DRVH resistance | Source, IDRVH = 50 mA | 1.6 | Ω | ||
Sink, IDRVH = 50 mA | 0.6 | |||||
RDRVL | DRVL resistance | Source, IDRVL = 50 mA | 0.9 | |||
Sink, IDRVL = 50 mA | 0.5 | |||||
INTERNAL BOOT STRAP SWITCH | ||||||
VF | Forward voltage | VVREG-VBST, TA = 25°C, IF = 10 mA | 0.1 | 0.2 | V | |
IVBST | VBST leakage current | TA = 25°C, VVBST = 33 V, VSW = 28 V | 0.01 | 1.5 | μA | |
ENABLE LOGIC THRESHOLD | ||||||
VL | EN low-level voltage | 0.5 | V | |||
VH | EN high-level voltage | 1.8 | V | |||
VHYST | EN hysteresis voltage | 0.22 | V | |||
ILEAK | EN input leakage current | -1 | 0 | 1 | μA | |
POWER GOOD COMPARATOR | ||||||
VPGTH | Powergood threshold | PGOOD in from higher | 105% | 108% | 111% | |
PGOOD in from lower | 89% | 92% | 95% | |||
PGOOD out to higher | 113% | 116% | 119% | |||
PGOOD out to lower | 81% | 84% | 87% | |||
IPG | PGOOD sink current | VPGOOD = 0.5 V | 6.9 | mA | ||
IPGLK | PGOOD leakage current | VPGOOD = 5.0 V | -1 | 0 | 1 | μA |
CURRENT DETECTION | ||||||
ITRIP | TRIP source current | TA = 25°C, VTRIP = 0.4 V, RDS(on) sensing | 9 | 10 | 11 | μA |
TCITRIP | TRIP source current temperature coefficient(1) | RDS(on) sensing | 4700 | ppm/°C | ||
VTRIP | TRIP voltage range | RDS(on) sensing | 0.2 | 3 | V | |
VOCLP | Positive current limit threshold | VTRIP = 3.0 V, RDS(on) sensing | 360 | 375 | 390 | mV |
VTRIP = 1.6 V, RDS(on) sensing | 190 | 200 | 210 | |||
VTRIP = 0.2 V, RDS(on) sensing | 20 | 25 | 30 | |||
VOCLN | Negative current limit threshold | VTRIP = 3.0 V, RDS(on) sensing | –390 | –375 | –360 | mV |
VTRIP = 1.6 V, RDS(on) sensing | –212 | –200 | –188 | |||
VTRIP = 0.2 V, RDS(on) sensing | –30 | –25 | –20 | |||
VZC | Zero cross detection offset | 0 | mV | |||
PROTECTIONS | ||||||
VVREGUVLO | VREG UVLO threshold voltage | Wake-up | 3.32 | V | ||
Shutdown | 3.11 | |||||
VOVP | OVP threshold voltage | OVP detect voltage | 117% | 120% | 123% | |
tOVPDLY | OVP propagation delay time | With 100-mV overdrive | 430 | ns | ||
VUVP | UVP threshold voltage | UVP detect voltage | 65% | 68% | 71% | |
THERMAL SHUTDOWN | ||||||
TSDN | Thermal shutdown threshold | Shutdown temperature | 140 | °C | ||
Hysteresis | 40 | |||||
LDO VOLTAGE | ||||||
VREG | LDO output voltage | VIN = 12 V, ILOAD = 10 mA | 4.5 | 5 | 5.5 | V |
VDOVREG | LDO low droop drop-out voltage | VIN = 4.5 V, ILOAD = 30 mA, TA = 25°C | 365 | mV | ||
ILDO(max) | LDO overcurrent limit(1) | VIN = 12 V, TA = 25°C | 152 | mA | ||
VDD UVLO VOLTAGE | ||||||
VDDUVLO | VDD UVLO voltage | VDDINUVLO<2:0> = 0xx | 10.2 | V | ||
VDDINUVLO<2:0> = 101 | 4.1 | 4.25 | 4.4 | |||
VDDINUVLO<2:0> = 110 | 6.0 | |||||
VDDINUVLO<2:0> = 111 | 8.1 | |||||
VDDHY-UVLO | VDD UVLO hysteresis voltage | 0°C ≤ TJ ≤ 85°C | 0.2 | V | ||
PMBus SCL and SDA INPUT BUFFER LOGIC THRESHOLDS | ||||||
VIL-PMBUS | SCL and SDA low-level input voltage(1) | 0°C ≤ TJ ≤ 85°C | 0.8 | V | ||
VIH-PMBUS | SCL and SDA high-level input voltage(1) | 0°C ≤ TJ ≤ 85°C | 2.1 | V | ||
VHY-PMBUS | SCL and SDA hysteresis voltage(1) | 0°C ≤ TJ ≤ 85°C | 240 | mV | ||
PMBus SDA and ALERT OUTPUT PULLDOWN | ||||||
VOL1-PMBUS | SDA and ALERT low-level output voltage(1) | VDDPMBus = 5.5 V,
RPULLUP = 1.1 kΩ, 0°C ≤ TJ ≤ 85°C |
0.4 | V | ||
VOL2-PMBUS | SDA and ALERT low-level output voltage(1) | VDDPMBus = 3.6 V,
RPULLUP = 0.7 kΩ, 0°C ≤ TJ ≤ 85°C |
0.4 | V |