SLUSB56B November   2012  – April 2019 TPS53819A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable and Soft-Start
      2. 7.3.2  Adaptive On-Time Control
      3. 7.3.3  Zero Crossing Detection
      4. 7.3.4  Output Discharge Control
      5. 7.3.5  Low-Side Driver
      6. 7.3.6  High-Side Driver
      7. 7.3.7  Power Good
      8. 7.3.8  Current Sense and Overcurrent Protection
      9. 7.3.9  Overvoltage and Undervoltage Protection
      10. 7.3.10 Out-of-Bound Protection
      11. 7.3.11 UVLO Protection
      12. 7.3.12 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Light-Load Condition in Auto-Skip Operation (Eco-mode)
      2. 7.4.2 Forced Continuous Conduction Mode
      3. 7.4.3 D-CAP2™ Mode
    5. 7.5 Programming
      1. 7.5.1 PMBus General Descriptions
      2. 7.5.2 PMBus Slave Address Selection
      3. 7.5.3 PMBus Address Selection
      4. 7.5.4 Supported Formats
        1. 7.5.4.1 Direct Format: Write
        2. 7.5.4.2 Combined Format: Read
        3. 7.5.4.3 Stop-Separated Reads
      5. 7.5.5 Supported PMBus Commands
      6. 7.5.6 Unsupported PMBus Commands
    6. 7.6 Register Maps
      1. 7.6.1  OPERATION [01h] (R/W Byte)
      2. 7.6.2  ON_OFF_CONFIG [02h] (R/W Byte)
      3. 7.6.3  WRITE_PROTECT [10h] (R/W Byte)
      4. 7.6.4  CLEAR_FAULTS [03h] (Send Byte)
      5. 7.6.5  STORE_DEFAULT_ALL [11h] (Send Byte)
      6. 7.6.6  RESTORE_DEFAULT_ALL [12h] (Send Byte)
      7. 7.6.7  STATUS_WORD [79h] (Read Word)
      8. 7.6.8  CUSTOM_REG (MFR_SPECIFIC_00) [D0h] (R/W Byte)
      9. 7.6.9  DELAY_CONTROL (MFR_SPECIFIC_01) [D1h] (R/W Byte)
      10. 7.6.10 MODE_SOFT_START_CONFIG (MFR_SPECIFIC_02) [D2h] (R/W Byte)
      11. 7.6.11 FREQUENCY_CONFIG (MFR_SPECIFIC_03) [D3h] (R/W Byte)
      12. 7.6.12 VOUT_ADJUSTMENT (MFR_SPECIFIC_04) [D4h] (R/W Byte)
      13. 7.6.13 Output Voltage Fine Adjustment Soft Slew Rate
      14. 7.6.14 VOUT_MARGIN (MFR_SPECIFIC_05) [D5h] (R/W Byte)
      15. 7.6.15 Output Voltage Margin Adjustment Soft-Slew Rate
      16. 7.6.16 UVLO_THRESHOLD (MFR_SPECIFIC_06) [D6h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Switching Frequency
        3. 8.2.2.3  Inductor (L1)
        4. 8.2.2.4  Output Capacitors (C10, C11, C12, C13, C14)
        5. 8.2.2.5  Input Capacitors (C1, C2, C3, C4, C5)
        6. 8.2.2.6  MOSFET (Q1, Q2)
        7. 8.2.2.7  VREG Bypass Capacitor (C18)
        8. 8.2.2.8  VDD Bypass Capacitor (C19)
        9. 8.2.2.9  VBST Capacitor (C7)
        10. 8.2.2.10 Snubber (C8 and R9)
        11. 8.2.2.11 Feedback Resistance, RFBH and RFBL (R17 and R18)
        12. 8.2.2.12 Overcurrent Limit (OCL) Setting Resistance (R10)
        13. 8.2.2.13 PMBus Device Address (R3 and R4)
        14. 8.2.2.14 PGOOD Pullup Resistor (R2)
        15. 8.2.2.15 SCL and SDA Pulldown Resistors (R14 and R15)
        16. 8.2.2.16 PMBus Pullup Resistors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1 Layout Guidelines

Note these design considerations before starting a layout work using TPS53819A

  • Inductor, VIN capacitors, VOUT capacitors and MOSFETs are the power components and should be placed on one side of the PCB (solder side). Other small signal components can be placed on another side (component side). At least one inner plane should be inserted, connected to ground, in order to shield and isolate the small signal traces from noisy power lines.
  • Place all sensitive analog traces and components such as FB, VO, TRIP, PGOOD, and EN away from high-voltage switching nodes such as SW, DRVL, DRVH or VBST to avoid coupling. Use internal layers as ground planes and shield feedback trace from power traces and components.
  • Keep PMBus interfacing signals away from the sensitive analog traces.
  • The DC/DC converter has several high-current loops. Minimize the area of these loops in order to suppress switching noise.
    • The path from the VIN capacitors through the high and low-side MOSFETs and back to the capacitors through ground, is the most important loop area to minimize. Connect the negative node of the VIN capacitors and the source of the low-side MOSFET at ground as close as possible.
    • The second important loop is the path from the low-side MOSFET through inductor and VOUT capacitors, and back to source of the low-side MOSFET through ground. Connect source of the low-side MOSFET and negative node of VOUT capacitors at ground as close as possible.
    • The third important loop is that of the gate driving system for the low-side MOSFET. To turn on the low-side MOSFET, high current flows from the VDRV capacitor through the gate driver and the low-side MOSFET, and back to negative node of the capacitor through ground. To turn off the low-side MOSFET, high current flows from gate of the low-side MOSFET through the gate driver and PGND of the device, and back to source of the low-side MOSFET through ground. Connect the negative node of the VREG capacitor, source of the low-side MOSFET and PGND of the device at ground as close as possible.
  • A separate AGND from the high-current loop PGND should be used for the return of the sensitive analog circuitry. The two grounds should connect at a single point as close to the GND pin as possible.
  • Minimize the current loop from the VDD and VREG pins through their respective capacitors to the GND pin.
  • Because the TPS53819A controls the output voltage referring to voltage across VOUT capacitor, the top-side resistor of the voltage divider should be connected to the positive node of the VOUT capacitor. In a same manner both bottom side resistor and GND of the device should be connected to the negative node of VOUT capacitor. The trace from these resistors to the VFB pin should be short and thin. Place on the component side and avoid vias between these resistors and the device.
  • Connect the overcurrent setting resistor from the TRIP pin to ground and make the connections as close as possible to the device. Avoid coupling a high-voltage switching node to the trace from the TRIP pin to RTRIP and from RTRIP to ground .
  • Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be as short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace and vias of at least 0.5 mm (20 mils) diameter along this trace.
  • The PCB trace defined as switch node, which connects to source of high-side MOSFET, drain of low-side MOSFET and high-voltage side of the inductor, should be as short and wide as possible.
  • Follow any layout considerations for the MOSFET provided by the MOSFET manufacturer.