7.3.1 Powergood

The TPS53915 has powergood output that indicates high when switcher output is within the target. The power-good function is activated after the soft-start operation is complete. If the output voltage becomes within ±8% of the target value, internal comparators detect the power-good state and the power-good signal becomes high after a 1-ms internal delay. If the output voltage goes outside of ±16% of the target value, the power-good signal becomes low after a 2-μs internal delay. The power-good output is an open-drain output and must be pulled-up externally.

7.3.2 D-CAP3 Control and Mode Selection

Figure 39. Internal RAMP Generation Circuit

The TPS53915 uses D-CAP3 mode control to achieve fast load transient while maintaining the ease-of-use feature. An internal RAMP is generated and fed to the VFB pin to reduce jitter and maintain stability. The amplitude of the ramp is determined by the R-C time-constant as shown in Figure 39. At different switching frequencies, (f_SW) the R-C time-constant varies to maintain relatively constant RAMP amplitude.

The default switching frequency (f_SW) is pre-set at 400 kHz. The switching frequency can be changed via PMBus function (see Table 13).

7.3.3 D-CAP3 Mode

From small-signal loop analysis, a buck converter using the D-CAP3 mode control architecture can be simplified as shown in Figure 40.

Figure 40. D-CAP3 Mode

The D-CAP3 control architecture includes an internal ripple generation network enabling the use of very low-ESR output capacitors such as multi-layered ceramic capacitors (MLCC). No external current sensing network or voltage compensators are required with D-CAP3 control architecture. The role of the internal ripple generation network is to emulate the ripple component of the inductor current information and then combine it with the voltage feedback signal to regulate the loop operation. For any control topologies supporting no external compensation design, there is a minimum and/or maximum range of the output filter it can support. The output filter used with the TPS53513 is a lowpass L-C circuit. This L-C filter has double pole that is described in Equation 1.

Equation 1.

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS53513. The low frequency L-C double pole has a 180 degree in phase. At the output filter frequency, the gain rolls off at a –40dB per decade rate and the phase drops rapidly. The internal ripple generation network introduces a high-frequency zero that reduces the gain roll off from –40dB to –20dB per decade and increases the phase to 90 degree one decade above the zero frequency.

The inductor and capacitor selected for the output filter must be such that the double pole of Equation 1 is located close enough to the high-frequency zero so that the phase boost provided by the high-frequency zero provides adequate phase margin for the stability requirement.

After identifying the application requirements, the output inductance should be designed so that the inductor peak-to-peak ripple current is approximately between 25% and 35% of the I_CC(max) (peak current in the application). Use Table 1 to help locate the internal zero based on the selected switching frequency. In general, where reasonable (or smaller) output capacitance is desired, Equation 2 can be used to determine the necessary output capacitance for stable operation.

Equation 2.

If MLCC is used, consider the derating characteristics to determine the final output capacitance for the design. For example, when using an MLCC with specifications of 10-µF, X5R and 6.3 V, the deratings by DC bias and AC bias are 80% and 50% respectively. The effective derating is the product of these two factors, which in this case is 40% and 4-µF. Consult with capacitor manufacturers for specific characteristics of the capacitors to be used in the system/applications.

Table 2 shows the recommended output filter range for an application design with the following specifications:

• Input voltage, V_IN = 12 V
• Switching frequency, f_SW = 600 kHz
• Output current, I_OUT = 8 A

The minimum output capacitance is verified by the small signal measurement conducted on the EVM using the following two criteria:

• Loop crossover frequency is less than one-half the switching frequency (300 kHz)
• Phase margin at the loop crossover is greater than 50 degrees

For the maximum output capacitance recommendation, simplify the procedure to adopt an unrealistically high output capacitance for this type of converter design, then verify the small signal response on the EVM using the following one criteria:

• Phase margin at the loop crossover is greater than 50 degrees

As indicated by the phase margin, the actual maximum output capacitance (C_OUT(max)) can continue to go higher. However, small signal measurement (bode plot) should be done to confirm the design.

Select a MODE pin configuration as shown in Table 3 to double the R-C time constant option for the maximum output capacitance design and application. Select a MODE pin configuration to use single R-C time constant option for the normal (or smaller) output capacitance design and application.

The MODE pin also selects SKIP-mode or FCCM-mode operation.

For higher output voltage at or above 2.0 V, additional phase boost might be required in order to secure sufficient phase margin due to phase delay/loss for higher output voltage (large on-time (t_ON)) setting in a fixed on time topology based operation.

A feedforward capacitor placing in parallel with R_UPPER is found to be very effective to boost the phase margin at loop crossover.

7.3.4 Sample and Hold Circuitry

Figure 41. Sample and Hold Circuitry (Patent Pending)

The sample and hold circuitry is the difference between D-CAP3 and D-CAP2. The sample and hold circuitry, which is an advance control scheme to boost output voltage accuracy higher on the TPS53915, is one of features of the TPS53915. The sample and hold circuitry generates a new DC voltage of CSN instead of the voltage which is produced by R_C2 and C_C2 which allows for tight output-voltage accuracy and makes the TPS53915 more competitive.

Figure 42. Continuous Conduction Mode (CCM) With Sample and Hold Circuitry

Figure 44. Continuous Conduction Mode (CCM) Without Sample and Hold Circuitry

Figure 46. Output Voltage vs Output Current

Figure 43. Discontinuous Conduction Mode (DCM) With Sample and Hold Circuitry

Figure 45. Discontinuous Conduction Mode (DCM) Without Sample and Hold Circuitry

Figure 47. Output Voltage vs Output Current

7.3.5 Adaptive Zero-Crossing

The TPS53915 uses an adaptive zero-crossing circuit to perform optimization of the zero inductor-current detection during skip-mode operation. This function allows ideal low-side MOSFET turn-off timing. The function also compensates the inherent offset voltage of the Z-C comparator and delay time of the Z-C detection circuit. Adaptive zero-crossing prevents SW-node swing-up caused by too-late detection and minimizes diode conduction period caused by too-early detection. As a result, the device delivers better light-load efficiency.

7.3.6 Forced Continuous-Conduction Mode

When the MODE pin is tied to the PGOOD pin through a resistor, the controller operates in continuous conduction mode (CCM) during light-load conditions. During CCM, the switching frequency maintained to an amost constant level over the entire load range which is suitable for applications requiring tight control of the switching frequency at the cost of lower efficiency.

7.3.7 Current Sense and Overcurrent Protection

The TPS53915 has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF state and the controller maintains the OFF state during the period that the inductor current is larger than the overcurrent trip level. In order to provide good accuracy and a cost-effective solution, the TPS53915 supports temperature compensated MOSFET R_DS(on) sensing. Connect the TRIP pin to GND through the trip-voltage setting resistor, R_TRIP. The TRIP terminal sources I_TRIP current, which is 10 μA typically at room temperature, and the trip level is set to the OCL trip voltage V_TRIP as shown in Equation 3.

Equation 3.

where

• V_TRIP is in mV
• R_TRIP is in kΩ
• I_TRIP is in µA

Equation 4 calculates the typical DC OCP level (typical low-side on-resistance [RDS(on)] of 5.9 mΩ should be used); in order to design for worst case minimum OCP, maximum low-side on-resistance value of 8 mΩ should be used. The inductor current is monitored by the voltage between the GND pin and SW pin so that the SW pin is properly connected to the drain terminal of the low-side MOSFET. I_TRIP has a 3000-ppm/°C temperature slope to compensate the temperature dependency of R_DS(on). The GND pin acts as the positive current-sensing node. Connect the GND pin to the proper current sensing device, (for example, the source terminal of the low-side MOSFET.)

Because the comparison occurs during the OFF state, V_TRIP sets the valley level of the inductor current. Thus, the load current at the overcurrent threshold, I_OCP, is calculated as shown in Equation 4.

Equation 4.

where

• R_DS(on) is the on-resistance of the low-side MOSFET
• R_TRIP is in kΩ

In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output voltage tends to decrease. Eventually, the output voltage crosses the undervoltage-protection threshold and shuts down.

7.3.8 Overvoltage and Undervoltage Protection

The TPS53915 monitors a resistor-divided feedback voltage to detect overvoltage and undervoltage. When the feedback voltage becomes lower than 68% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins counting. After 1 ms, the TPS53915 latches OFF both high-side and low-side MOSFETs drivers. The UVP function enables after soft-start is complete.

When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes high and the circuit latches OFF the high-side MOSFET driver and turns on the low-side MOSFET until reaching a negative current limit. Upon reaching the negative current limit, the low-side FET is turned off and the high-side FET is turned on again for a minimum on-time. The TPS53915 operates in this cycle until the output voltage is pulled down under the UVP threshold voltage for 1 ms. After the 1-ms UVP delay time, the high-side FET is latched off and low-side FET is latched on. The fault is cleared with a reset of VDD or by re-toggling EN pin.

7.3.9 Out-Of-Bounds Operation (OOB)

The TPS53915 has an out-of-bounds (OOB) overvoltage protection that protects the output load at a much lower overvoltage threshold of 8% above the target voltage. OOB protection does not trigger an overvoltage fault, so the device is not latched off after an OOB event. OOB protection operates as an early no-fault overvoltage-protection mechanism. During the OOB operation, the controller operates in forced PWM mode only by turning on the low-side FET. Turning on the low-side FET beyond the zero inductor current quickly discharges the output capacitor thus causing the output voltage to fall quickly towards the setpoint. During the operation, the cycle-by-cycle negative current limit is also activated to ensure the safe operation of the internal FETs.

7.3.10 UVLO Protection

The TPS53915 monitors the voltage on the VDD pin. If the VDD pin voltage is lower than the UVLO off-threshold voltage, the switch mode power supply shuts off. If the VDD voltage increases beyond the UVLO on-threshold voltage, the controller turns back on. UVLO is a non-latch protection.

7.3.11 Thermal Shutdown

The TPS53915 monitors internal temperature. If the temperature exceeds the threshold value (typically 140°C), TPS53915 shuts off. When the temperature falls approximately 40°C below the threshold value, the device turns on. Thermal shutdown is a non-latch protection.

7.4.1 Auto-Skip Eco-Mode Light-Load Operation

While the MODE pin is pulled to GND directly or through a 150-kΩ resistor, the TPS53915 device automatically reduces the switching frequency at light-load conditions to maintain high efficiency. This section describes the operation in detail.

As the output current decreases from heavy-load condition, the inductor current also decreases until the rippled valley of the inductor current touches zero level. Zero level is the boundary between the continuous-conduction and discontinuous-conduction modes. The synchronous MOSFET turns off when this zero inductor current is detected. As the load current decreases further, the converter runs into discontinuous-conduction mode (DCM). The on-time is maintained to a level approximately the same as during continuous-conduction mode operation so that discharging the output capacitor with a smaller load current to the level of the reference voltage requires more time. The transition point to the light-load operation I O(LL) (for example: the threshold between continuous- and discontinuous-conduction mode) is calculated as shown in Equation 5.

Equation 5.

where

• f SW is the PWM switching frequency

TI recommends only using ceramic capacitors for Auto-skip mode.

7.4.2 Forced Continuous-Conduction Mode

When the MODE pin is tied to the PGOOD pin through a resistor, the controller operates in continuous conduction mode (CCM) during light-load conditions. During CCM, the switching frequency maintained to an almost constant level over the entire load range which is suitable for applications requiring tight control of the switching frequency at the cost of lower efficiency.

7.5.1 The PMBus General Descriptions

The TPS53915 has seven internal custom user-accessible 8-bit registers. The PMBus interface has been designed for program flexibility, supporting a direct format for write operation. Read operations are supported for both combined format and stop separated format. While there is no auto increment/decrement capability in the TPS53915 PMBus logic, a tight software loop can be designed to randomly access the next register, regardless of which register was accessed first. The START and STOP commands frame the data packet and the REPEAT START condition is allowed when necessary.

The device can operate in either standard mode (100 kb/s) or fast mode (400 kb/s).

7.5.2 PMBus Slave Address Selection

The seven-bit slave address is 001A₃A₂A₁A₀x, where A₃A₂A₁A₀ is set by the ADDR pin on the device. Bit 0 is the data direction bit, i.e., 001A₃A₂A₁A₀0 is used for write operation and 001A₃A₂A₁A₀1 is used for read operation.

7.5.3 PMBus Address Selection

The TPS53915 allows up to 16 different chip addresses for PMBus communication, with the first three bits fixed as 001. The address selection process is defined by the resistor divider ratio from VREG pin to ADDR pin, and the address detection circuit starts to work only after VDD input supply has risen above its UVLO threshold. The table below lists the divider ratio and some example resistor values. The 1% tolerance resistors with typical temperature coefficient of ±100 ppm/°C are recommended. Higher performance resistors can be used if tighter noise margin is required for more reliable address detection, as shown in Table 4.

7.5.4 Supported Formats

The supported formats are described in this section.

7.5.5 Supported PMBus Commands

The TPS53915 supports the PMBus commands shown in Table 5 only. Not all features of each PMBus command are supported. The CLEAR_FAULTS, STORE_DEFAULT_ALL and RESTORE_DEFAULT_ALL commands have no data bytes. The non-volatile memory (NVM) cells inside the TPS53915 can permanently store some registers.

7.5.6 CLEAR_FAULTS [03h] (Send Byte)

The CLEAR_FAULTS command is used to clear any fault bits in the STATUS_WORD and STATUS_BYTE registers that have been set. This command clears all bits in all status registers. Simultaneously, the TPS53915 releases its ALERT signal output if the device is asserting the ALERT signal. If the FAULT condition is still present when the bit is cleared, the fault bits shall immediately be set again, and the ALERT signal should also be re-asserted.

The CLEAR_FAULTS does not cause a unit that has latched off for a FAULT condition to restart. Units that have been shut down for a FAULT condition can be restarted with one of the following conditions.

• The output is commanded through the EN pin and/or ON_OFF bit based on the ON_OFF_CONFIG setting to turn off and then to turn back on.
• VDD power is cycled for TPS53915

The CLEAR_FAULT command is used to clear the fault bits in the STATUS_WORD and STATUS_BYTE commands, and to release the ALERT pin. It is recommended not to send CLEAR_FAULT command when there is no fault to cause the ALERT pin to pull down.

7.5.7 STORE_DEFAULT_ALL [11h] (Send Byte)

The STORE_DEFAULT_ALL command instructs TPS53915 to copy the entire contents of the operating memory to the corresponding locations in the NVM. The updated contents in the non-volitile memory (NVM)s become the new default values. The STORE_DEFAULT_ALL command can be used while the device is operating. However, the device may be unresponsive during the copy operation with unpredictable results. (see PMBus Power System Management Protocol Specificaiton, Part II - Command Language, Revision, 1.2, 6 Sept. 2010. www.powerSIG.org). It is recommended not to exceed 1000 write/erase cycles for non-volatile memory (NVM).

7.5.8 RESTORE_DEFAULT_ALL [12h] (Send Byte)

The RESTORE_DEFAULT_ALL command instructs TPS53915 to copy the entire contents of the NVMs to the corresponding locations in the operating memory. The values in the operating memory are overwritten by the value retrieved from the NVM. It is permitted to use the RESTORE_DEFAULT_ALL command while the device is operating. However, the device may be unresponsive during the copy operation with unpredictable results.

7.5.9 STATUS_WORD [79h] (Read Word)

The TPS53915 does not support all functions of the STATUS_WORD command. A list of supported functions appears in Table 9. A status bit reflects the current state of the converter. Status bit becomes high when the specified condition has occurred and goes low when the specified condition has disappeared. A flag bit is a latched bit that becomes high when the specified condition has occurred and does not go back low when the specified condition has disappeared. STATUS_BYTE command is a subset of the STATUS_WORD command, or more specifically the lower byte of the STATUS_WORD.

The latched flags of faults can be removed or corrected only until one of the following conditions occurs:

• The device receives a CLEAR_FAULTS command.
• The output is commanded through the EN pin and/or ON_OFF bit based on the ON_OFF_CONFIG setting to turn off and then to turn back on
• VDD power is cycled for TPS53915

If the FAULT condition remains present when the bit is cleared, the fault bits are immediately set again, and the ALERT signal is re-asserted.

TPS53915 supports the ALERT pin to notify the host of FAULT conditions. Therefore, the best practice for monitoring the fault conditions from the host is to treat the ALERT pin as an interrupt source for triggering the corresponding interrupt service routine. It is recommended not to keep polling the STATUS_WORD or STATUS_BYTE registers from the host to reduce the firmware overhead of the host.

7.5.10 CUSTOM_REG (MFR_SPECIFIC_00) [D0h] (R/W Byte)

Custom register 0 provides the flexibility for users to store any desired non-volatile information. For example, users can program this register to track versions of implementation or other soft identification information. The details of each setting are listed in Table 10.

7.5.11 DELAY_CONTROL (MFR_SPECIFIC_01) [D1h] (R/W Byte)

Custom register 1 provides software control over key timing parameters of the controller: Power-on delay (POD) time and power-good delay (PGD) time. The details of each setting are listed in Table 11.

7.5.12 MODE_SOFT_START_CONFIG (MFR_SPECIFIC_02) [D2h] (R/W Byte)

Custom register 2 provides software control over mode selection and soft-start time (t_SS). The details of each setting are listed in Table 12.

Figure 48 shows the soft-start timing diagram of TPS53915 with the programmable power-on delay time (t_POD), soft-start time (t_SST), and PGOOD delay time (t_PGD). During the soft-start time, the controller remains in discontinuous conduction mode (DCM), and then switches to forced continuous conduction mode (FCCM) at the end of soft-start if CM bit (MODE_SOFT_START_CONFIG<0>) is set.

Figure 48. Programmable Soft-Start Timing

7.5.13 FREQUENCY_CONFIG (MFR_SPECIFIC_03) [D3h] (R/W Byte)

Custom register 3 provides software control over frequency setting (FS). The details of FS setting are listed in Table 13.

7.5.14 VOUT_ADJUSTMENT (MFR_SPECIFIC_04) [D4h] (R/W Byte)

Custom register 4 provides ouput voltage adjustment (VOA) in ±0.75% steps, with a total range of ±9%. When fine adjustment is used together with the margin setting, the change in the output voltage is determined by the multiplication of the two settings.

7.5.15 Output Voltage Fine Adjustment Soft Slew Rate

To prevent sudden buildup of voltage across inductor, output voltage fine adjustment setting cannot change output voltage instantaneously. The internal reference voltage must slew slowly to its final target, and SST<1:0> is used to provide further programmability. The details of output voltage fine adjustment slew rate are shown in Table 15.

7.5.16 VOUT_MARGIN (MFR_SPECIFIC_05) [D5h] (R/W Byte)

Custom register 5 provides output voltage margin high (VOMH) and output voltage margin low (VOML) settings. This register works in conjunction with PMBus OPERATION command to raise or lower the output voltage by a specified amount. This register settings described in Table 16 are also used together with the fine adjustment setting described in Table 14. For example, setting fine adjustment to +9% and margin to +12% changes the output by +22.08%, whereas setting fine adjustment to –9% and margin to –9% change the output by –17.19%

7.5.17 Output Voltage Margin Adjustment Soft-Slew Rate

Similar to the output voltage fine adjustment, margin adjustment also cannot change output voltage instantaneously. The soft-slew rate of margin adjustment is also programmed by SST<1:0>. The details are listed in Table 17.

Figure 49 shows the timing diagram of the output voltage adjustment via PMBus. After receiving the write command of VOUT_ADJUSTMENT (MFR_SPECIFIC_04), the output voltage starts to be adjusted after t_P delay time (about 50 μs). The time duration t_DAC for each DAC step change can be controlled by SST bits (MODE_SOFT_START_CONFIG<3:2:> from 4 μs to 32 μs.

Figure 49. Output Voltage Adjustment via PMBus

The margining function is enabled by setting the OPERATION command, and the margining level is determined by the VOUT_MARGIN (MFR_SPECIFIC_05) command. Figure 50 and Figure 51 illustrate the timing diagrams of the output voltage margining via PMBus. Figure 50 shows setting the margining level first, and then enabling margining by writing OPERATION command. After the OPERATION margin high command enables the margin high setting (VOMH<3:0>), the output voltage starts to be adjusted after t_P delay time (about 50 μs). The time duration t_DAC for each DAC step change can be controlled by SST bits (MODE_SOFT_START_CONFIG<3:2>) from 4 μs to 32 μs.

As shown in Figure 51, the margining function is enabled first by a write command of OPERATION. The output voltage starts to be adjusted toward the default margin high level after t_P delay. Because the margining function has been enabled, the output voltage can be adjusted again by sending a different margin high level with a write command of VOUT_MARGIN. The time duration t_DAC for each DAC step change can be also controlled by SST bits (MODE_SOFT_START_CONFIG<3:2>) from 4 μs to 32 μs.

Figure 50. Setting the Margining Level First

Figure 51. Enabling Margining First

7.5.18 UVLO_THRESHOLD (MFR_SPECIFIC_06) [D6h]

Custom register 6 provides some limited programmability of input supply UVLO threshold, as described in Table 18. The default turn-on UVLO threshold is 4.25 V.